Datasheet

78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE
R01UH0028EJ0400 Rev.4.00 94
Sep 27, 2010
Table 3-8. Special Function Register List: 78K0/KA2-L (25-pin and 32-pin products) (5/5)
Bit No.
Number of Bits
Manipulated
Simultaneously
Address Symbol
7 6 5 4 3 2 1 0
R/W
1 8 16
After
Reset
Reference
page
FFC0H to
FFDFH
− − − − − − − − − − − − − − −
FFE0H IF0L
<SREIF6> <PIF5> <PIF4> <PIF3> <PIF2> 0 <PIF0> <LVIIF>
R/W
√ √ 00H 598
FFE1H
IF0
IF0H
<TMIF010> <TMIF000> 0 0 <TMIFH1> <CSIIF10> <STIF6> <SRIF6>
R/W
√ √
√
00H 598
FFE2H IF1L
0 0 0 0
<TMIF51> 0 0 <ADIF> R/W √ √ 00H 598
FFE3H
IF1
IF1H
0 0 0
0 0 0 0 <IICAIF0> R/W √ √
√
00H 598
FFE4H MK0L
<SREMK6> <PMK5> <PMK4> <PMK3> <PMK2> 1 <PMK0> <LVIMK>
R/W
√ √ FFH 606
FFE5H
MK0
MK0H
<TMMK
010>
<TMMK
000>
1 1
<TMMK
H1>
<CSIM
K10
<STMK
6>
<SRMK
6>
R/W
√ √
√
FFH 606
FFE6H MK1L
1 1 1 1
<TMMK
51>
1 1 <ADMK>
R/W
√ √ FFH 606
FFE7H
MK1
MK1H
1 1 1 1 1 1 1
<IICA
MK0>
R/W
√ √
√
FFH 606
FFE8H PR0L
<SREMK6> <PPR5> <PPR4> <PPR3> <PPR2> 1 <PPR0> <LVIPR>
R/W
√ √ FFH 613
FFE9H
PR0
PR0H
<TMPR
010>
<TMPR
000>
1 1
<TMP
RH1>
<CSIPR
10>
<STPR
6>
<SRPR
6>
R/W
√ √
√
FFH 613
FFEAH PR1L
1 1
1 1
<TMP
R51>
1 1 <ADPR>
R/W
√ √ FFH 613
FFEBH
PR1
PR1H
1 1 1 1 1 1 1
<IICAP
R0>
R/W
√ √
√
FFH 613
FFECH to
FFEFH
− − − − − − − − − − − − − − −
FFF0H IMS RAM2 RAM1 RAM0 0 ROM3 ROM2 ROM1 ROM0 R/W − √ − CFH
Note
699
FFF1H to
FFFAH
− − − − − − − − − − − − − − −
FFFBH
PCC 0 0 0 0 0 PCC2 PCC1 PCC0 R/W
√ √ − 01H
204
Note Reset signal generation makes the setting of the ROM area undefined. Therefore, set the value corresponding
to each product as indicated in Table 3-1 after release of reset.
Remark For a bit name enclosed in angle brackets (<>), the bit name is defined as a reserved word in the RA78K0,
and is defined as an sfr variable using the #pragma sfr directive in the CC78K0.
<R>