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User’s Manual

All information contained in these materials, including products and product specifications,

represents information on the product at the time of publication and is subject to change by

Renesas Electronics Corp. without notice. Please review the latest information published by

Renesas Electronics Corp. through various means, including the Renesas Electronics Corp.

website (http://www.renesas.com).

78K0/Kx2-L

User’s Manual: Hardware

Rev.4.00 Sep 2010

8-Bit Single-Chip Microcontrollers

www.renesas.com

Summary of content (822 pages)

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User’s Manual 8 78K0/Kx2-L User’s Manual: Hardware 8-Bit Single-Chip Microcontrollers All information contained in these materials, including products and product specifications, represents information on the product at the time of publication and is subject to change by Renesas Electronics Corp. without notice. Please review the latest information published by Renesas Electronics Corp. through various means, including the Renesas Electronics Corp. website (http://www.renesas.com). www.renesas.com Rev.
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Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
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NOTES FOR CMOS DEVICES (1) VOLTAGE APPLICATION WAVEFORM AT INPUT PIN: Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
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How to Use This Manual Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/Kx2-L microcontrollers and design and develop application systems and programs for these devices. The target products are as follows.
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Conventions Related Documents Data significance: Active low representations: Note: Caution: Remark: Numerical representations: Higher digits on the left and lower digits on the right ××× (overscore over pin and signal name) Footnote for item marked with Note in the text Information requiring particular attention Supplementary information ...×××× or ××××B Binary ...×××× Decimal Hexadecimal ...××××H The related documents indicated in this publication may include preliminary versions.
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Documents Related to Development Tools (Software) Document Name RA78K0 Ver.3.80 Assembler Package User’s Manual Note 1 Document No. Operation U17199E Language U17198E Structured Assembly Language Note 1 78K0 Assembler Package RA78K0 Ver.4.01 Operating Precautions (Notification Document) CC78K0 Ver.3.70 C Compiler User’s Manual Note 2 Operation U17197E ZUD-CD-07-0181-E U17201E Language U17200E Note 2 78K0 C Compiler CC78K0 Ver. 4.
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CONTENTS CHAPTER 1 OUTLINE............................................................................................................................... 1 1.1 Features........................................................................................................................................... 1 1.2 Ordering Information...................................................................................................................... 4 1.3 Pin Configuration (Top View) .......................
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3.3.1 Relative addressing....................................................................................................................... 106 3.3.2 Immediate addressing ................................................................................................................... 107 3.3.3 Table indirect addressing .............................................................................................................. 108 3.3.4 Register addressing ...........................................
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5.6.3 Example of controlling subsystem clock........................................................................................ 226 5.6.4 Example of controlling internal low-speed oscillation clock ........................................................... 228 5.6.5 Clocks supplied to CPU and peripheral hardware ......................................................................... 229 5.6.6 CPU clock status transition diagram.........................................................................
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CHAPTER 9 WATCHDOG TIMER ....................................................................................................... 363 9.1 9.2 9.3 9.4 Functions of Watchdog Timer................................................................................................... 363 Configuration of Watchdog Timer ............................................................................................ 364 Register Controlling Watchdog Timer...................................................................
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CHAPTER 14 SERIAL INTERFACE UART6 ...................................................................................... 446 14.1 14.2 14.3 14.4 Functions of Serial Interface UART6 ...................................................................................... 446 Configuration of Serial Interface UART6................................................................................ 451 Registers Controlling Serial Interface UART6.......................................................................
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17.3 Registers Controlling Interrupt Functions............................................................................. 596 17.4 Interrupt Servicing Operations ............................................................................................... 629 17.4.1 Maskable interrupt acknowledgment ........................................................................................... 629 17.4.2 Software interrupt request acknowledgment ..............................................................
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CHAPTER 25 FLASH MEMORY .......................................................................................................... 699 25.1 25.2 25.3 25.4 Internal Memory Size Switching Register .............................................................................. 699 Writing with Flash Memory Programmer ............................................................................... 700 Programming Environment ........................................................................................
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CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS........................................................... 777 CHAPTER 31 CAUTIONS FOR WAIT................................................................................................. 778 31.1 Cautions for Wait...................................................................................................................... 778 31.2 Peripheral Hardware That Generates Wait ............................................................................
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R01UH0028EJ0400 Rev.4.00 Sep 27, 2010 78K0/Kx2-L RENESAS MCU CHAPTER 1 OUTLINE 1.
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78K0/Kx2-L CHAPTER 1 OUTLINE { Timer • 16-bit timer/event counter … PPG output, capture input, external event counter input • 8-bit timer H … PWM output • 8-bit timer/event counter 5 … PWM output, external event counter input • Watchdog timer … Operable with low-speed internal oscillation clock • Real-time counter … Available to count up in year, month, week, day, hour, minute, and second units Item 16-bit timer/event 8-bit timer Products 78K0/KY2-L (16 pins) 1 ch Real-time counter 78K0/KA2-L
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78K0/Kx2-L CHAPTER 1 OUTLINE { On-chip debug function …Available to control for the target device, and to reference memory { Assembler and C language supported { Development tools • Support for full-function emulator (IECUBE), and simplified emulator (MINICUBE2) { Power supply voltage: VDD = 1.8 to 5.5 V { Operating ambient temperature: TA = –40 to +85°C R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 1 OUTLINE 1.2 Ordering Information [Part Number] μ PD78F05 x y ΔΔ - ××× -AX Semiconductor -AX x F Product contains no lead in any area (Terminal free finish is Ni/Pd/Au plating) ΔΔ - ××× Package Type 5 MA-FAA 16-pin plastic SSOP (5.72 mm (225)) 6 MC-CAA 20-pin plastic SSOP (7.62 mm (300)) FC-2N2 25-pin plastic FLGA (3x3) K8-3B4 32-pin plastic WQFN (5x5) 7 MC-CAB 30-pin plastic SSOP (7.
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78K0/Kx2-L CHAPTER 1 OUTLINE [List of Part Number] 78K0/Kx2-L Package Part Number Microcontrollers 78K0/KY2-L 78K0/KA2-L 78K0/KB2-L 78K0/KC2-L 16-pin plastic SSOP μPD78F0550MA-FAA-AX, 78F0551MA-FAA-AX, 78F0552MA-FAA-AX, (5.72 mm (225)) 78F0555MA-FAA-AX, 78F0556MA-FAA-AX, 78F0557MA-FAA-AX 20-pin plastic SSOP μPD78F0560MC-CAA-AX, 78F0561MC-CAA-AX, 78F0562MC-CAA-AX, (7.
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78K0/Kx2-L CHAPTER 1 OUTLINE 1.3 Pin Configuration (Top View) 1.3.1 78K0/KY2-L • 16-pin plastic SSOP (5.
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78K0/Kx2-L CHAPTER 1 OUTLINE 1.3.2 78K0/KA2-L (1) 20-pin plastic SSOP (7.
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78K0/Kx2-L CHAPTER 1 OUTLINE (2) 25-pin plastic FLGA (3x3) (1/2) Bottom View Top View INDEX MARK INDEX MARK A B C D E 1 2 3 1 A 4 5 5 2 VDD VSS 4 3 2 3 RESET/ P125 1 4 5 P61/RXD6 ANI4/P24 /SDAA0 B REGC C P35/SCK11 D P33 P121/X1/TOOLC0 P122/X2/EXCLK (/TI000)(/INTP0) /TOOLD0 P60/TXD6/SCLA0 ANI6/P26 P36/SI11 P37/SO11 P02/SSI11/INTP5 ANI5/P25 P00/TI000/INTP0 ANI3/P23 ANI2/P22 ANI0/P20 /AMP0+ (/TOH1)(/TI51) E P34/INTP4 (/TOH1)(/TI51) P32/INTP3 /TOOLD1 P31/INTP2
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78K0/Kx2-L CHAPTER 1 OUTLINE (2) 25-pin plastic FLGA (3x3) (2/2) Note μPD78F0565, 78F0566, 78F0567 (products with operational amplifier) only Cautions 1. VSS functions alternately as the ground potential of the A/D converter. Be sure to connect VSS to a stabilized GND (= 0 V). 2. Connect the REGC pin to VSS via a capacitor (0.47 to 1 μF). 3. ANI0/P20/AMP0-, ANI1/P21/AMP0OUT/PGAIN, ANI2/P22/AMP0+, and ANI3/P23 to ANI6/P26 are set in the analog input mode after release of reset. 4.
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78K0/Kx2-L CHAPTER 1 OUTLINE (3) 32-pin plastic WQFN (5x5) (2/2) AMP0- Note , AMP0+ Note : Amplifier Input RESET : Amplifier Output RxD6 : Receive Data : Programmable Gain SCK11 : Serial Clock Input/Output Amplifier Input SCLA0 : Serial Clock Input/Output ANI0 to ANI10 : Analog Input SDAA0 : Serial Data Input/Output AVREF : Analog Reference Voltage SI11 : Serial Data Input AVSS : Analog Ground SO11 : Serial Data Output : External Clock Input SSI11 : Serial Interface Chip
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78K0/Kx2-L CHAPTER 1 OUTLINE 1.3.3 78K0/KB2-L • 30-pin plastic SSOP (7.
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78K0/Kx2-L CHAPTER 1 OUTLINE 1.3.
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78K0/Kx2-L CHAPTER 1 OUTLINE (1) 40-pin plastic WQFN (6x6) (2/2) AMP0- Note Note Note Note , AMP0+ , AMP1+ AMP1- AMP0OUT Note AMP1OUT Note , : Amplifier Input , , Note PGAIN : Amplifier Output : Programmable Gain Amplifier Input ANI0 to ANI6, ANI8 to ANI10 : Analog Input REGC : Regulator Capacitance RESET : Reset RxD6 : Receive Data SCLA0, SCK10, SCK11 : Serial Clock Input/Output SDAA0 : Serial Data Input/Output SI10, SI11 : Serial Data Input SO10, SO11 : Serial Data O
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78K0/Kx2-L CHAPTER 1 OUTLINE ANI7/P27 ANI6/P26 ANI5/P25 ANI4/P24 ANI3/P23 ANI2/P22/AMP0+Note ANI1/P21/AMP0OUTNote/PGAINNote ANI0/P20/AMP0-Note P01/TI010/TO00 P00/TI000 P120/INTP0/EXLVI(/SO11) (2) 44-pin plastic LQFP (10x10) (1/2) 44 43 42 41 40 39 38 37 36 35 34 P41/RTC1HZ(/SI11) 1 33 AVSS P40/RTCCL/RTCDIV(/SCK11) 2 32 AVREF RESET/P125 3 31 P10/SCK10/ANI8/AMP1-Note P124/XT2/EXCLKS 4 30 P11/SI10/ANI9/AMP1OUTNote P123/XT1 5 29 P12/SO10/ANI10/AMP1+Note IC 6 28 P13/TxD6 P12
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78K0/Kx2-L CHAPTER 1 OUTLINE (2) 44-pin plastic LQFP (10x10) (2/2) Note AMP0- Note AMP1- , AMP0+ Note , AMP1+ Note AMP0OUT Note AMP1OUT Note Note PGAIN , : Amplifier Input , : : REGC: Regulator Capacitance RESET : Reset RTC1HZ : Real-time Counter Amplifier Output Correction Clock (1 Hz) Programmable Gain Output Amplifier Input RTCCL : Real-time Counter ANI0 to ANI10 : Analog Input Clock (32 kHz Original AVREF : Analog Reference Oscillation) Output Voltage AVSS : Analo
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78K0/Kx2-L CHAPTER 1 OUTLINE VDD VSS REGC P121/X1/TOOLC0 P122/X2/EXCLK/TOOLD0 IC P123/XT1 P124/XT2/EXCLKS RESET/P125 P40/RTCCL/RTCDIV(/SCK11) P41/RTC1HZ(/SI11) P120/INTP0/EXLVI(/SO11) (3) 48-pin plastic LQFP (fine pitch) (7x7) (1/2) 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 P42/PCL/SSI11/INTP6 P00/TI000 P01/TI010/TO00 P02/INTP7 ANI0/P20/AMP0-Note ANI1/P21/AMP0OUTNote/PGAINNote ANI2/P22/AMP0+Note ANI3/P23 ANI4/
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78K0/Kx2-L CHAPTER 1 OUTLINE (3) 48-pin plastic LQFP (fine pitch) (7x7) (2/2) Note AMP0- Note AMP1- , AMP0+ Note , AMP1+ Note AMP0OUT Note AMP1OUT Note Note PGAIN , : , REGC : Regulator Capacitance Amplifier Input RESET : Reset Amplifier Output RTC1HZ : Real-time Counter : : Correction Clock (1 Hz) Programmable Gain Amplifier Input Output RTCCL : Real-time Counter ANI0-ANI10 : Analog Input Clock (32 kHz Original AVREF : Analog Reference Oscillation) Output Voltage AVSS :
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78K0/Kx2-L CHAPTER 1 OUTLINE 1.4 Block Diagram 1.4.
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78K0/Kx2-L CHAPTER 1 OUTLINE 1.4.
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78K0/Kx2-L CHAPTER 1 OUTLINE (2) 25-pin products TI000/P00 16-bit TIMER/ EVENT COUNTER 00 (TI000)/P121 PORT 0 2 P00, P02 PORT 2 7 P20-P26 PORT 3 7 P31-P37 PORT 6 2 P60, P61 PORT 12 3 P121, P122, P125 RxD6/P61 8-bit TIMER/ EVENT COUNTER 51 (TI51)/P00 (TI51)/P34 (TOH1)/P00 (TOH1)/P34 8-bit TIMER H1 INTERNAL LOW-SPEED OSCILLATOR WATCHDOG TIMER RxD6/P61 TxD6/P60 SERIAL INTERFACE UART6 LINSEL SDAA0/P61 SCLA0/P60 SERIAL INTERFACE IICA SCK11/P35 SI11/P36 SO11/P37 SERIAL
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78K0/Kx2-L CHAPTER 1 OUTLINE (3) 32-pin products TO00/TI010/P01 (TI000)/P121 (TI000)/P125 RxD6/P61 16-bit TIMER/ EVENT COUNTER 00 PORT 0 2 P01, P02 PORT 2 8 P20-P27 PORT 3 7 P31-P37 PORT 6 2 P60, P61 PORT 7 3 P70-P72 PORT 12 3 P121, P122, P125 8-bit TIMER/ EVENT COUNTER 51 (TOH1)/P34 8-bit TIMER H1 INTERNAL LOW-SPEED OSCILLATOR WATCHDOG TIMER RxD6/P61 TxD6/P60 SERIAL INTERFACE UART6 LINSEL SDAA0/P61 SCLA0/P60 SERIAL INTERFACE IICA SCK11/P35 SI11/P36 SO11/P37 SERI
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78K0/Kx2-L CHAPTER 1 OUTLINE 1.4.
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78K0/Kx2-L CHAPTER 1 OUTLINE 1.4.
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78K0/Kx2-L CHAPTER 1 OUTLINE 1.5 Outline of Functions (1/2) Item 78K0/KY2-L 78K0/KA2-L 78K0/KB2-L 78K0/KC2-L (μPD78F055x) (μPD78F056x) (μPD78F057x) (μPD78F058x) 16 Pins Internal Flash memory memory (self-programming supported ) High-Speed RAM Clock Main Memory space 20 Pins 25 Pins 32 Pins 30 Pins 4 KB to 16 KB 8 KB to 32 KB 384 bytes to 768 bytes 512 bytes to 1 KB 40 Pins 44 Pins 64 KB High-speed system (crystal/ceramic oscillation, external clock input) 1 to 10 MHz: VDD = 2.
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78K0/Kx2-L CHAPTER 1 OUTLINE (2/2) Item Serial UART interface IICA 78K0/KY2-L 78K0/KA2-L 78K0/KB2-L 78K0/KC2-L (μPD78F055x) (μPD78F056x) (μPD78F057x) (μPD78F058x) 16 Pins 20 Pins – – 32 Pins 30 Pins 40 Pins 44 Pins 48 Pins 1 ch 1 ch CSI 10-bit A/D converter 25 Pins 4 ch 6 ch Note 1 ch (CSI11 7 ch ) 11 ch Note 1 ch (CSI10) 2 ch (CSI10, CSI11 ) 7 ch 10 ch 11 ch 11 ch 11 13 4 6 (AVREF = 1.8 to 5.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are two types of pin I/O buffer power supplies: AVREF and VDD. The relationship between these power supplies and the pins is shown below. Table 2-1.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS 2.1.1 78K0/KY2-L (1) Port functions: 78K0/KY2-L Function Name P00 I/O I/O Function Port 0. After Reset Input port 2-bit I/O port. P01 Alternate Function TI000/INTP0 TO00/TI010 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P20 I/O Port 2. Analog input 4-bit I/O port. P21 ANI0/AMP0- Note ANI1/AMP0OUT Input/output can be specified in 1-bit units.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS (2) Non-port functions : 78K0/KY2-L Function Name ANI0 I/O Input Function A/D converter analog input After Reset Analog input Alternate Function P20/AMP0- Note Note P21/AMP0OUT ANI1 / Note PGAIN ANI2 P22/AMP0+ ANI3 Note P23 Note Input AMP0- AMP0+ Operational amplifier 0 input Analog input Note AMP0OUT Note PGAIN P20/ANI0 P22/ANI2 Note Output Operational amplifier 0 output Input PGA (programmable gain amplifier) input P21/ANI1/PGAIN Analog in
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS 2.1.2 78K0/KA2-L (1) Port functions: 78K0/KA2-L (20 pins) Function Name P00 I/O Function Port 0. I/O After Reset Input port 2-bit I/O port. P01 Alternate Function TI000/INTP0 TO00/TI010 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P20 Port 2. I/O Analog input 6-bit I/O port. P21 ANI0/AMP0- Note ANI1/AMP0OUT Input/output can be specified in 1-bit units.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS (2) Non-port functions: 78K0/KA2-L (20 pins) (2/2) Function Name Note Input AMP0- AMP0+ I/O Function Operational amplifier 0 input After Reset Analog input Note AMP0OUT Note PGAIN Alternate Function P20/ANI0 P22/ANI2 Note Output Operational amplifier 0 output Input PGA (programmable gain amplifier) input P21/ANI1/PGAIN Analog input P21/ANI1/ AMP0OUT INTP0 Input External interrupt request input for which the valid edge Input port (rising edge, fallin
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS (3) Port functions: 78K0/KA2-L (25, 32 pins) Function Name P00 P01 Note 1 I/O I/O Note 2 Function Port 0. After Reset Input port Alternate Function TI000 Note 1 /INTP0 2-bit I/O port. (/TOH1) Input/output can be specified in 1-bit units. TO00 Note 1 Note 1 (/TI51) Note 2 /TI010 Note 1 Note 2 Use of an on-chip pull-up resistor can be specified by a P02 SSI11/INTP5 software setting. I/O P20 Port 2. Analog input 8-bit I/O port.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS (4) Non-port functions: 78K0/KA2-L (25, 32 pins) (1/2) Function Name I/O Input ANI0 Function A/D converter analog input After Reset Analog input Alternate Function P20/AMP0- Note 3 Note 3 P21/AMP0OUT ANI1 / Note 3 PGAIN ANI2 P22/AMP0+ ANI3 to ANI6 P23 to P26 ANI7 Note 2 P27 Note 2 ANI8 Note 2 P70 Note 2 ANI9 Note 2 P71 Note 2 P72 Note 2 ANI10 Note 2 AMP0- Note 3 AMP0+ PGAIN Input Operational amplifier 0 input Analog input Note 3
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS (4) Non-port functions: 78K0/KA2-L (25, 32 pins) (2/2) Function Name I/O Function After Reset Alternate Function SCK11 I/O Clock input/output for CSI10 SI11 Input Serial data input to CSI10 P36 SO11 Output Serial data output from CSI10 P37 Input Chip select input to CSI11 Input External count clock input to 16-bit timer/event counter 00 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter 00 SSI11 Note 1 TI000 (
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS 2.1.3 78K0/KB2-L (1) Port functions: 78K0/KB2-L Function Name P00 I/O I/O Function Port 0. After Reset Input port 2-bit I/O port. P01 Alternate Function TI000 TI010/TO00 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P10 I/O Port 1. Input port 8-bit I/O port.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS (2) Non-port functions: 78K0/KB2-L (1/2) Function Name ANI0 I/O Input Function A/D converter analog input After Reset Analog input Alternate Function P20/AMP0- Note Note P21/AMP0OUT ANI1 / Note PGAIN ANI2 P22/AMP0+ ANI3 P23 Input port ANI8 Note Note P10/SCK10/AMP1- ANI9 P11/SI10/AMP1OUT ANI10 P12/SO10/AMP1+ Note AMP0- AMP0+ Input Analog input P20/ANI0 Operational amplifier 1 input Input port P10/ANI8/SCK10 Note P12/ANI10/SO10 AMP0OUT Not
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS (2) Non-port functions: 78K0/KB2-L (2/2) Function Name I/O Function After Reset Alternate Function I/O Clock input/output for CSI10 SI10 Input Serial data input to CSI10 P11/ANI9/AMP1OUT SO10 Output Serial data output from CSI10 P12/ANI10/AMP1+ TI000 Input External count clock input to 16-bit timer/event counter 00 Capture trigger input to capture registers (CR000, CR010) of 16-bit timer/event counter 00 TI010 Input port Input port Capture trigger in
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS 2.1.4 78K0/KC2-L (1) Port functions: 78K0/KC2-L (1/2) Function Name P00 I/O I/O Function Port 0. After Reset Input port 3-bit I/O port. P01 Alternate Function TI000 TI010/TO00 Input/output can be specified in 1-bit units. P02 Note 1 Note 1 INTP7 Use of an on-chip pull-up resistor can be specified by a software setting. P10 I/O P11 Port 1. Input port Note 2 / 8-bit I/O port. SCK10 Input/output can be specified in 1-bit units.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS (1) Port functions: 78K0/KC2-L (2/2) Function Name I/O Port 6. I/O P60 P61 After Reset Input port SCLA0/SCK11/ INTP11 Input/output can be specified in 1-bit units. SDAA0/SI11/INTP10 SO11/INTP9 1-bit units. Note 3 Alternate Function 4-bit I/O port. Input of P60 and P61 can be set to SMBus input buffer in P62 P63 Function INTP8 Output of P60 to P63 can be set to N-ch open-drain output Note 3 (VDD tolerance).
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS (2) Non-port functions : 78K0/KC2-L (2/4) Function Name ANI8 I/O Input Function A/D converter analog input After Reset Input port Alternate Function Note 2 P10/SCK10/AMP1P11/SI10/ ANI9 AMP1OUT Note 2 Note 2 ANI10 P12/SO10/AMP1+ Note 2 Operational amplifier 0 input AMP0- AMP0+ Operational amplifier 1 input AMP1- Input port Note 2 AMP0OUT Note 2 AMP1OUT Note 2 Note 2 PGAIN P20/ANI0 P22/ANI2 Note 2 AMP1+ Analog input Note 2 P10/ANI8/SCK10 P
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS (2) Non-port functions : 78K0/KC2-L (3/4) Function Name Input KR0 to KR3 KR4 Note 1 PCL Note 1 , KR5 I/O Function Key interrupt input After Reset Input port Note 1 Output Clock output (for output of high-speed system clock, Input port subsystem clock) RTCDIV RTCCL Note 3 Output Note 3 RTC1HZ Note 3 − REGC Alternate Function P70 to P73 P74 Note 1 P42 Note 1 , P75 /SSI11 INTP6 Real-time counter clock (32 kHz divided frequency) Input port
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS (2) Non-port functions: 78K0/KC2-L (4/4) Function Name TI50 I/O Input TI51 External count clock input to 8-bit timer/event counter 50 After Reset Input port External count clock input to 8-bit timer/event counter 51 TO00 Output TO50 Output TO51 TOH0 Function 16-bit timer/event counter 00 output Input port 8-bit timer/event counter 50 output Input port TOH1 8-bit timer H0 output − Connecting resonator for main system clock Input port P15 Input port
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions Remark The pins mounted depend on the product. Refer to 1.3 Pin Configuration (Top View) and 2.1 Pin Function List. 2.2.1 P00 to P02 (port 0) P00 to P02 function as an I/O port. These pins also function as timer I/O, external interrupt request input, and chip select input of serial interface. The timer I/O can be assigned to P00 of the 78K0/KA2-L (25-pin products) by setting the port alternate switch control register (MUXSEL).
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS (g) SSI11 This is a chip select input pin of serial interface CSI11. 2.2.2 P10 to P17 (port 1) P10 to P17 function as an I/O port. These pins also function as pins for A/D converter analog input, operational amplifier I/O, external interrupt request input, serial interface data I/O, clock I/O, and timer I/O.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS (e) SO10 This is a serial data output pin of serial interface CSI10. (f) SCK10 This is a serial clock I/O pin of serial interface CSI10. (g) RxD6 This is a serial data input pin of serial interface UART6. (h) TxD6 This is a serial data output pin of serial interface UART6. (i) TI50 This is a pin for inputting an external count clock to 8-bit timer/event counter 50. (j) TO50 This is a timer output pin of 8-it timer/event counter 50.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS (1) Port mode P20 to P27 function as an I/O port. P20 to P27 can be set to input or output port in 1-bit units using port mode register 2 (PM2). (2) Control mode P20 to P27 function as A/D converter analog input, operational amplifier I/O, and PGA input. (a) ANI0 to ANI7 These are A/D converter analog input pins. When using these pins as analog input pins, refer to (5) ANI0/P20 to ANI7/P27 and ANI8/P10 to ANI10/P12 in 12.6 Cautions for A/D Converter.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS The following operation modes can be specified in 1-bit units. (1) Port mode P30 to P37 function as an I/O port. P30 to P37 can be set to input or output port in 1-bit units using port mode register 3 (PM3). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 3 (PU3).
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS 2.2.5 P40 to P42 (port 4) P40 to P42 function as an I/O port. These pins also function as pins for external interrupt request input, real-time counter clock output, real-time counter correction clock output, and chip select input of serial interface. The clock I/O and data input of the serial interface can be assigned to P40 and P41 of the 78K0/KC2-L (44-pin and 48pin products) respectively by setting the port alternate switch control register (MUXSEL).
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS (h) SSI11 This is a chip select input pin of serial interface CSI11. 2.2.6 P60 to P63 (port 6) P60 to P63 function as an I/O port. These pins also function as pins for serial interface data I/O, clock I/O, and external interrupt request input. Input to the P60 and P61 pins can be specified through a normal input buffer or an SMBus input buffer in 1-bit units, using port input mode register 6 (PIM6).
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS (g) SO11 This is a serial data output pin for serial interface CSI11. (h) INTP8 to INTP11 These are external interrupt request input pins for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. 2.2.7 P70 to P75 (port 7) P70 to P75 function as an I/O port. These pins also function as pins for A/D converter analog input and key interrupt input pins.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS 2.2.8 P120 to P125 (port 12) P120 functions as an I/O port. P121 to P125 function as an Input port.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS (a) INTP0 This functions as an external interrupt request input (INTP0) for which the valid edge (rising edge, falling edge, or both rising and falling edges) can be specified. (b) EXLVI This is a potential input pin for external low-voltage detection. (c) X1, X2 These are pins for connecting a resonator for main system clock. (d) EXCLK This is an external clock input pin for main system clock. (e) XT1, XT2 These are pins for connecting a resonator for subsystem clock.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS 2.2.9 AVREF, AVSS, VDD, VSS These are the power supply/ground pins. 78K0/KY2-L 78K0/KA2-L 78K0/KB2-L 78K0/KC2-L (μPD78F055x) (μPD78F056x) (μPD78F057x) (μPD78F058x) 16 Pins 20, 25, 32 Pins 30 Pins 40, 44, 48 Pins AVREF AVREF − − AVREF AVREF AVSS AVSS VDD VDD VDD VDD VSS VSS VSS VSS (a) AVREF This is the A/D converter reference voltage input pin and the positive power supply pin of port 2 and A/D converter.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS (a) REGC This is a pin for connecting regulator output (2.0 V/2.4 V) stabilization capacitance for internal operation. Connect this pin to VSS via a capacitor (0.47 to 1 μF). However, when using the STOP mode that has been entered since operation of the internal high-speed oscillation clock and external main system clock, 0.47 μF is recommended. Also, use a capacitor with good characteristics, since it is used to stabilize internal voltage.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Tables 2-2 to 2-6 show the types of pin I/O circuits and the recommended connections of unused pins. Refer to Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-2. Pin I/O Circuit Types (78K0/KY2-L) Pin Name I/O Circuit Type 5-AQ P00/TI000/INTP0 I/O Input: I/O Independently connect to VDD or VSS via a resistor. Output: Leave open.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS Table 2-3. Pin I/O Circuit Types (78K0/KA2-L (20-pin products)) Pin Name I/O Circuit Type 5-AQ P00/TI000/INTP0 I/O Input: I/O Independently connect to VDD or VSS via a resistor. Output: Leave open. P01/TO00/TI010 ANI0/P20/AMP0- Recommended Connection of Unused Pins Note 1 ANI1/P21/AMP0OUT 11-P Note 1 Independently connect to AVREF or VSS via a resistor.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS Table 2-4. Pin I/O Circuit Types (78K0/KA2-L (25-pin and 32-pin products)) Pin Name P00 Note 1 /TI000 INTP0 P01 / I/O I/O 5-AQ Note 1 Note 2 /TO00 TI010 I/O Circuit Type Note 1 Recommended Connection of Unused Pins Input: Independently connect to VDD or VSS via a resistor. Output: Leave open.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS Table 2-5. Pin I/O Circuit Types (78K0/KB2-L) Pin Name I/O Circuit Type P00/TI000 I/O Input: I/O 5-AQ Independently connect to VDD or VSS via a resistor. Output: Leave open.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS Table 2-6. Pin I/O Circuit Types (78K0/KC2-L) (1/2) Pin Name I/O Circuit Type 5-AQ P00/TI000 Note 1 /INTP7 I/O Recommended Connection of Unused Pins Input: Independently connect to VDD or VSS via a resistor. Output: Leave open.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS Table 2-6. Pin I/O Circuit Types (78K0/KC2-L) (2/2) Pin Name I/O Circuit Type P60/SCLA0/SCK11/INTP11 I/O Input: I/O 5-AS Note 3 /INTP8 the output latch of the port to 0. 5-AR P62/SO11/INTP9 Independently connect to VDD or VSS via a resistor. Output: Leave this pin open at low-level output after clearing P61/SDAA0/SI11/INTP10 P63 Recommended Connection of Unused Pins Note 3 Input: 5-AQ P70/KR0 Independently connect to VDD or VSS via a resistor.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS Figure 2-1.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS Figure 2-1.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS Figure 2-1.
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78K0/Kx2-L CHAPTER 2 PIN FUNCTIONS Figure 2-1. Pin I/O Circuit List (4/4) Type 42-A VDD pullup enable P-ch IN input enable SCHMIT reset reset mask R01UH0028EJ0400 Rev.4.
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K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Products in the 78K0/Kx2-L microcontrollers can access a 64 KB memory space. Figures 3-1 to 3-4 show the memory maps. Caution Reset signal generation makes the setting of the ROM area undefined. Therefore, set the value corresponding to each product as indicated below after release of reset. Table 3-1.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Figure 3-1.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Figure 3-2.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Figure 3-3.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Figure 3-4.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-2.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE The internal program memory space is divided into the following areas. (1) Vector table area The 64-byte area 0000H to 003FH is reserved as a vector table area. The program start addresses for branch upon reset or generation of each interrupt request are stored in the vector table area. Of the 16-bit address, the lower 8 bits are stored at even addresses and the higher 8 bits are stored at odd addresses. Table 3-4.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area A 5-byte area of 0080H to 0084H and 1080H to 1084H can be used as an option byte area. Set the option byte at 0080H to 0084H when the boot swap is not used, and at 0080H to 0084H and 1080H to 1084H when the boot swap is used. For details, refer to CHAPTER 24 OPTION BYTE.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/Kx2-L microcontrollers, based on operability and other considerations.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Figure 3-6.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Figure 3-7.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Figure 3-8.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0/Kx2-L microcontrollers incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1). It is reset (0) in all other cases.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Figure 3-12. Data to Be Saved to Stack Memory (a) PUSH rp instruction (when SP = FEE0H) SP SP FEE0H FEDEH FEE0H FEDFH Register pair higher FEDEH Register pair lower (b) CALL, CALLF, CALLT instructions (when SP = FEE0H) SP SP FEE0H FEDEH FEE0H FEDFH PC15 to PC8 FEDEH PC7 to PC0 (c) Interrupt, BRK instructions (when SP = FEE0H) SP SP R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Figure 3-13. Data to Be Restored from Stack Memory (a) POP rp instruction (when SP = FEDEH) SP SP FEE0H FEDEH FEE0H FEDFH Register pair higher FEDEH Register pair lower (b) RET instruction (when SP = FEDEH) SP SP FEE0H FEDEH FEE0H FEDFH PC15 to PC8 FEDEH PC7 to PC0 (c) RETI, RETB instructions (when SP = FEDDH) SP SP R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The generalpurpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH area. Special function registers can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions. The manipulatable bit units, 1, 8, and 16, depend on the special function register type. Each manipulation bit unit can be specified as follows.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously FF00H P0 − FF01H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 P01 P00 − − − − − − − page Address Reference Table 3-6.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 6 5 4 3 2 1 0 − − − − − − − − − FF53H ASIS6 0 0 0 0 0 PE6 FE6 FF54H − − − − − − − − FF55H ASIF6 0 0 0 0 0 0 FF56H CKSR6 0 0 0 0 TPS63 TPS62 FF57H BRGC6 FF51H page Address Reference Table 3-6.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 6 5 4 3 2 1 0 1 8 16 page Address Reference Table 3-6.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously FF00H P0 − FF01H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 P01 P00 − − − − − − − page Address Reference Table 3-7.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 6 5 4 3 2 1 0 − − − − − − − − − FF53H ASIS6 0 0 0 0 0 PE6 FE6 FF54H − − − − − − − FF55H ASIF6 0 0 0 0 0 0 FF56H CKSR6 0 0 0 0 FF57H BRGC6 FF51H page Address Reference Table 3-7.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 6 5 4 3 2 1 0 1 8 16 page Address Reference Table 3-7.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously P0 7 6 5 4 3 2 1 0 0 0 0 0 0 P02 P01 P00 Note 2 Note 1 FF00H − FF01H FF02H P2 page Address Reference Table 3-8.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously FF23H PM3 7 6 5 4 3 2 1 0 PM37 PM36 PM35 PM34 PM33 PM32 PM31 1 1 8 16 R/W √ √ − FFH page Address Reference Table 3-8.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously FF42H − FF43H TMC51 FF44H to − 7 6 5 4 3 2 1 0 − − − − − − − − 0 0 0 0 0 0 − − − − − − page Address Reference Table 3-8.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 6 5 4 3 2 1 0 1 8 16 page Address Reference Table 3-9.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously FF23H PM3 7 6 5 4 3 2 1 0 1 1 1 1 PM33 PM32 PM31 PM30 R/W 1 8 16 √ √ − FFH page Address Reference Table 3-9.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously FF4CH to − 7 6 5 4 3 2 1 0 − − − − − − − − 0 0 0 0 0 0 ISC1 PS61 PS60 CL6 − − page Address Reference Table 3-9.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 6 5 4 3 2 P02 Note1 1 0 P01 P00 page Address Reference Table 3-10.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. 7 6 5 4 3 FF20H PM0 1 1 1 1 1 FF21H PM1 PM17 PM16 PM15 PM14 PM13 FF22H PM2 PM27 FF23H PM3 FF24H PM4 FF25H PER0 FF26H Note2 Number of Bits Manipulated Simultaneously R/W 2 1 0 Note 1 PM01 PM00 R/W PM12 PM11 PM10 R/W PM02 After Reset 1 8 16 √ √ − √ √ − page Address Reference Table 3-10.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 FF40H FF41H CKS Note1 CR51 FF42H − FF43H TMC51 FF44H to − 6 5 4 3 2 1 0 page Address Reference Table 3-10.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 6 506 5 4 0 0 FF6BH TMC50 FF6CH TMHMD1 FF6DH TMCYC1 0 0 FF6EH KRM 0 0 FF6FH RTCC2 OE2> DIV> − − − FF7AH SIO11 − FF7BH − − CKS12 CKS11 CKS10 3 2 1 0 50> 501 50> TMMD TMMD
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE Symbol Bit No. R/W Number of Bits After Manipulated Reset Simultaneously 7 6 5 4 3 2 1 0 page Address Reference Table 3-10.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by contents of the program counter (PC) and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11 instruction is branched to the 0800H to 0FFFH area.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE 3.3.4 Register addressing [Function] Register pair (AX) contents to be specified with an instruction word are transferred to the program counter (PC) and branched. This function is carried out when the BR AX instruction is executed. [Illustration] 7 rp 0 7 A 15 0 X 8 7 0 PC 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes of an operation code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address. This addressing can be carried out for all of the memory spaces.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all of the memory spaces.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all of the memory spaces.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the B or C register contents as a positive number to 16 bits. A carry from the 16th bit is ignored.
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78K0/Kx2-L CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions There are two types of pin I/O buffer power supplies: AVREF and VDD. The relationship between these power supplies and the pins is shown below. Table 4-1.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions (78K0/KY2-L) Function Name P00 I/O I/O Function Port 0. After Reset Input port 2-bit I/O port. P01 Alternate Function TI000/INTP0 TO00/TI010 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P20 I/O Port 2. Analog input 4-bit I/O port. P21 ANI0/AMP0- Note ANI1/AMP0OUT Input/output can be specified in 1-bit units.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Table 4-3. Port Functions (78K0/KA2-L (20-pin products)) Function Name P00 I/O I/O Function Port 0. After Reset Input port 2-bit I/O port. P01 Alternate Function TI000/INTP0 TO00/TI010 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P20 I/O Port 2. Analog input 6-bit I/O port. P21 ANI0/AMP0- Note ANI1/AMP0OUT Input/output can be specified in 1-bit units.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Table 4-4. Port Functions (78K0/KA2-L (25-pin and 32-pin products)) Function Name P00 P01 Note 1 I/O I/O Note 2 Function Port 0. After Reset Input port Alternate Function TI000 Note 1 /INTP0 2-bit I/O port. (/TOH1) Input/output can be specified in 1-bit units. TO00 Note 1 Note 1 (/TI51) Note 2 /TI010 Note 1 Note 2 Use of an on-chip pull-up resistor can be specified by a P02 SSI11/INTP5 software setting. I/O P20 Port 2.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Table 4-5. Port Functions (78K0/KB2-L) Function Name P00 I/O I/O Function Port 0. After Reset Input port 2-bit I/O port. P01 Alternate Function TI000 TI010/TO00 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P10 I/O Port 1. Input port 8-bit I/O port. P11 Note /SCK10 Note ANI9/AMP1OUT /SI10 Input/output can be specified in 1-bit units.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Table 4-6. Port Functions (78K0/KC2-L) (1/2) Function Name P00 I/O I/O Function Port 0. After Reset Input port 3-bit I/O port. P01 Alternate Function TI000 TI010/TO00 Input/output can be specified in 1-bit units. P02 Note 1 Note 1 INTP7 Use of an on-chip pull-up resistor can be specified by a software setting. P10 I/O P11 Port 1. Input port Note 2 / 8-bit I/O port. SCK10 Input/output can be specified in 1-bit units.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Table 4-6. Port Functions (78K0/KC2-L) (2/2) Function Name I/O I/O P60 P61 Port 6. After Reset Input port SCLA0/SCK11/ INTP11 Input/output can be specified in 1-bit units. SDAA0/SI11/INTP10 SO11/INTP9 1-bit units. Note 2 Alternate Function 4-bit I/O port. Input of P60 and P61 can be set to SMBus input buffer in P62 P63 Function Note 2 INTP8 Output of P60 to P63 can be set to N-ch open-drain output (VDD tolerance).
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports include the following hardware. Table 4-7.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS 4.2.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-2. Block Diagram of P01 VDD WRPU PU0 PU01 P-ch Alternate function Selector Internal bus RD WRPORT P0 Output latch (P01) P01/TI010/TO00 WRPM PM0 PM01 Alternate function P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WR××: Write signal R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-3. Block Diagram of P02 VDD WRPU PU0 PU02 P-ch RD Selector Internal bus Alternate function WRPORT P0 Output latch (P02) WRPM P02/INTP7 (78K0/KC2-L) P02/SSI11/INTP5 (78K0/KA2-L) PM0 PM02 P0: Port register 0 PU0: Pull-up resistor option register 0 PM0: Port mode register 0 RD: Read signal WR××: Write signal R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS 4.2.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Table 4-9. Setting Functions of P11/ANI9/AMP1OUT Pin ADPC1 Register Digital I/O PM1 Register Input mode OPAMP1E bit 0 selection ADS Register Selects ANI9. Setting prohibited Does not select ANI9. Digital input − 1 Output mode 0 Input mode Setting prohibited Does not select ANI9. Digital output − 0 Setting prohibited Selects ANI9. 1 Analog I/O P11/ANI9/AMP1OUT Pin Selects ANI9.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-4.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-4.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-5. Block Diagram of P11 (1/2) (1) Products without operational amplifier of 78K0/KB2-L and 78K0/KC2-L ADPC1 VDD ADPCS9 WRPU PU1 P-ch PU11 Alternate function Selector Internal bus RD WRPORT P1 Output latch (P11) P11/ANI9/SI10 WRPM PM1 PM11 A/D converter P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 ADPC1: A/D port configuration register 1 RD: Read signal WR××: Write signal R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-5.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-6. Block Diagram of P12 (1/2) (1) Products without operational amplifier of 78K0/KB2-L and 78K0/KC2-L ADPC1 VDD ADPCS10 WRPU PU1 P-ch PU12 Selector Internal bus RD WRPORT P1 Output latch (P12) P12/ANI10/SO10 WRPM PM1 PM12 Alternate function A/D converter P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 ADPC1: A/D port configuration register 1 RD: Read signal WR××: Write signal R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-6.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-7. Block Diagram of P13 VDD WRPU PU1 PU13 P-ch Selector Internal bus RD WRPORT P1 Output latch (P13) P13/TxD6 WRPM PM1 PM13 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR××: Write signal R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-8. Block Diagram of P14 VDD WRPU PU1 PU14 P-ch Alternate function Selector Internal bus RD WRPORT P1 Output latch (P14) P14/RxD6 WRPM PM1 PM14 P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR××: Write signal R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-9. Block Diagram of P15 VDD WRPU PU1 PU15 P-ch Internal bus Selector RD WRPORT P1 Output latch (P15) P15/TOH0 WRPM PM1 PM15 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR××: Write signal R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-10. Block Diagram of P16 and P17 VDD WRPU PU1 PU16, PU17 P-ch Alternate function Selector Internal bus RD WRPORT P1 Output latch (P16, P17) P16/TOH1/INTP5, P17/TI50/TO50 WRPM PM1 PM16, PM17 Alternate function P1: Port register 1 PU1: Pull-up resistor option register 1 PM1: Port mode register 1 RD: Read signal WR××: Write signal R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS 4.2.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Table 4-11. Setting Functions of P21/ANI1/AMP0OUT/PGAIN Pin ADPC0 PM2 Register OPAMP0E PGAEN bit bit Register Digital I/O Input mode − 0 selection Output mode 1 − 0 − Input mode 0 0 P21/ANI1/AMP0OUT/PGAIN Pin Selects ANI1. Setting prohibited Does not select ANI1. Digital input − Setting prohibited Selects ANI1. Setting prohibited Does not select ANI1.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Reset signal generation sets port 2 to analog input. Figures 4-11 to 4-14 show block diagrams of port 2. Caution Make the AVREF pin the same potential as the VDD pin when port 2 is used as a digital port. Figure 4-11.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-12.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-13. Block Diagram of P22 (1) Products without operational amplifier Internal bus Selector RD WRPORT P2 Output latch (P22) P22/ANI2 WRPM PM2 PM22 A/D converter (2) Products with operational amplifier Selector Internal bus RD WRPORT P2 Output latch (P22) P22/ANI2/AMP0+ WRPM PM2 PM22 A/D converter Operational amplifier (+) input P2: Port register 2 PM2: Port mode register 2 RD: Read signal WR××: Write signal R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-14. Block Diagram of P23-P27 Selector Internal bus RD WRPORT P2 Output latch (P23 to P27) P23/ANI3 to P27/ANI7 WRPM PM2 PM23 to PM27 A/D converter P2: Port register 2 PM2: Port mode register 2 RD: Read signal WR××: Write signal R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS 4.2.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-15.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-16.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-17. Block Diagram of P37 VDD WRPU PU3 PU37 P-ch Alternate function Selector Internal bus RD WRPORT P3 Output latch (P37) P37/SO11 WRPM PM3 PM37 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR××: Write signal R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-18. Block Diagram of P35 VDD WRPU PU3 PU35 P-ch Alternate function Internal bus Selector RD WRPORT P3 Output latch (P35) P35/SCK11 WRPM PM3 PM35 Alternate function P3: Port register 3 PU3: Pull-up resistor option register 3 PM3: Port mode register 3 RD: Read signal WR××: Write signal R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 4 78K0/KY2-L 78K0/KA2-L 78K0/KB2-L 78K0/KC2-L (μPD78F057x) (μPD78F056x) (μPD78F057x) (μPD78F058x) 16 Pins 20, 25, 32 Pins 30 Pins 40 Pins − − − − − − − − − − − 44 Pins 48 Pins P40/RTCCL/ P40/RTCCL/ RTCDIV(/SCK11) RTCDIV(/SCK11) P41/RTC1HZ P41/RTC1HZ (/SI11) (/SI11) − − P42/PCL/SSI11/ INTP6 Remark Functions in parentheses ( ) can be assigned by setting the port alternate switch control register (MUXSEL).
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-19.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-20. Block Diagram of P41 VDD WRPU PU4 PU41 P-ch MUXSEL RD Selector Alternate function Input signal from P61/SI11 Selector Internal bus CSISEL WRPORT P4 Output latch (P41) P41/RTC1HZ (/SI11) WRPM PM4 PM41 Alternate function Figure 4-21.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS 4.2.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-22.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-23.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-24. Block Diagram of P62 VDD WRPU PU6 PU62 P-ch Alternate function Selector Internal bus RD WRPORT POM6 POM62 P6 Output latch (P62) P62/SO11/INTP9 WRPM PM6 PM62 Alternate function P6: Port register 6 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 POM6: Port output mode register 6 RD: Read signal WR××: Write signal R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-25. Block Diagram of P63 VDD WRPU PU6 PU63 P-ch Alternate function Selector Internal bus RD POM6 POM63 WRPORT P6 Output latch (P63) P63/INTP8 WRPM PM6 PM63 P6: Port register 6 PU6: Pull-up resistor option register 6 PM6: Port mode register 6 POM6: Port output mode register 6 RD: Read signal WR××: Write signal R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 7 78K0/KY2-L 78K0/KA2-L 78K0/KB2-L 78K0/KC2-L (μPD78F057x) (μPD78F056x) (μPD78F057x) (μPD78F058x) 16 Pins 20, 25 Pins 32 Pins 30 Pins 40, 44 Pins 48 Pins − − P70/ANI8 − P70/KR0 P70/KR0 − − P71/ANI9 − P71/KR1 P71/KR1 − − P72/ANI10 − P72/KR2 P72/KR2 − − − − P73/KR3 P73/KR3 − − − − − P74/KR4 − − − − − P75/KR5 Port 7 is an I/O port with an output latch.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-26.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS 4.2.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Cautions 1. When using the P121 to P124 pins to connect a resonator for the main system clock (X1, X2) or subsystem clock (XT1, XT2), or to input an external clock for the main system clock (EXCLK) or subsystem clock (EXCLKS), the X1 oscillation mode, XT1 oscillation mode, or external clock input mode must be set by using the clock operation mode select register (OSCCTL) (for details, refer to 5.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-27.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-28. Block Diagram of P121 to P124 OSCCTL OSCSEL/ OSCSELS RD Internal bus P122/X2/EXCLK/TOOLD0, P124/XT2/EXCLKS OSCCTL EXCLK, OSCSEL/ EXCLKS, OSCSELS RD P121/X1/TOOLC0, P123/XT1 OSCCTL: Clock operation mode select register RD: Read signal WR××: Write signal R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-29. Block Diagram of P125 VDD WRPU PU12 PU125 P-ch Internal bus RD P125/RESET Internal reset WRPM RSTMASK RSTM PU12: Pull-up resistor option register 12 RD: Read signal WR××: Write signal RSTMASK: Reset pin mode register Caution Because RESET/P125 is set in the external reset input immediately after release of reset, if a reset signal is generated during low level input, the reset status continues until the input rises to the high level.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following eight types of registers.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-31.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-32.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-33.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-34.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS (2) Port registers (Pxx) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is read. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 4-35.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-36.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-37.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-38.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-39.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PUxx) These registers specify whether the on-chip pull-up resistors are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in these registers.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-42.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-44.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS (5) Port output mode register 6 (POM6) This register sets the output mode of P60 to P63 in 1-bit units. 2 During I C communication, set POM60 and POM61 to 1. In the 78K0/KY2-L and 78K0/KA2-L, clear POM60 to 0 when using the P60/TxD6/SCLA0 pin as the data output of serial interface UART6. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 4-46.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Note (7) A/D port configuration registers 0, 1 Note (ADPC0, ADPC1 ) ADPC0 switches the P20/AMP0-/ANI0 to P27/ANI7 pins to digital I/O or analog I/O of port. Each bit of ADPC0 corresponds to a pin of port 2 and can be specified in 1-bit units. Note ADPC1 switches the P10/AMP1-/ANI8 to P12/AMP1+/ANI10 or P70/ANI8 to P72/ANI10 pins to digital I/O or analog I/O of port.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-48.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Note (8) Port alternate switch control register (MUXSEL) MUXSEL of 78K0/KA2-L (25-pin products) assigns TOH1, TI51, TI000, and INTP0 pins. By default, INTP0 and TI000 are assigned to P00, while TI51 and TOH1 have no assignment setting. MUXSEL of 78K0/KA2-L (32-pin products) assigns TOH1, TI000, and INTP0 pins. By default, INTP0 and TI000 and TOH1 have no assignment setting.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Figure 4-49. Format of Port Alternate Switch Control Register (MUXSEL) (2/2) (2) 78K0/KA2-L (32-pin products) Address: FF39H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 MUXSEL INTP0SEL1 INTP0SEL0 TM00SEL1 TM00SEL0 0 0 0 TMHSEL0 INTP0SEL1 INTP0SEL0 0 0 External interrupt input (INTP0) pin function assignment No INTP0 function assignment. 0 1 Assign INTP0 to the P121 pin as the alternate function.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. 4.4.1 Writing to I/O port (1) Output mode A value is written to the output latch by a transfer instruction, and the output latch contents are output from the pin. Once data is written to the output latch, it is retained until data is written to the output latch again. The data of the output latch is cleared when a reset signal is generated.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS 4.5 Settings of Port Mode Register and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register and output latch as shown in Tables 4-14 to 4-18. Table 4-14.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Table 4-14. Settings of Port Mode Register and Output Latch When Using Alternate Function (78K0/KY2-L) (2/2) Pin Name Alternate Function Function Name P121 X1 P122 X2 − − Note 1 TOOLD0 Note 2 P125 Input RESET × × × × × × Input × × I/O × × Input × × Note 1 EXCLK P×× I/O Note 1 TOOLC0 PM×× Notes 1.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Table 4-15.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Table 4-15. Settings of Port Mode Register and Output Latch When Using Alternate Function (78K0/KA2-L (20-pin products)) (2/2) Pin Name Alternate Function Function Name P121 X1 P122 X2 − − Note 1 TOOLD0 Note 2 P125 Input RESET × × × × × × Input × × I/O × × Input × × Note 1 EXCLK P×× I/O Note 1 TOOLC0 PM×× Notes 1.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Table 4-16.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Table 4-16.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Table 4-17.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Table 4-17.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Table 4-18.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Table 4-18.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS Table 4-18.
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78K0/Kx2-L CHAPTER 4 PORT FUNCTIONS 4.6 Cautions on 1-Bit Manipulation Instruction for Port Register n (Pn) When a 1-bit manipulation instruction is executed on a port that provides both input and output functions, the output latch value of an input port that is not subject to manipulation may be written in addition to the targeted bit. Therefore, it is recommended to rewrite the output latch when switching a port from input mode to output mode.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable. (1) Main system clock <1> X1 oscillator This circuit oscillates a clock of fX = 1 to 10 MHz by connecting a resonator to X1 and X2. Oscillation can be stopped by executing the STOP instruction or using the main OSC control register (MOC).
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR (3) Internal low-speed oscillation clock (clock for watchdog timer) • Internal low-speed oscillator This circuit oscillates a clock of fIL = 30 kHz (TYP.). After a reset release, the internal low-speed oscillation clock always starts operating. Oscillation can be stopped by using the internal oscillation mode register (RCM) when “internal low-speed oscillator can be stopped by software” is set by option byte.
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78K0/Kx2-L Internal bus Main clock mode register (MCM) Main OSC control register (MOC) Clock operation mode select register (OSCCTL) EXCLK OSCSEL MCS MSTOP Main clock mode register (MCM) Oscillation stabilization time select register (OSTS) OSTS2 OSTS1 OSTS0 Processor clock control register (PCC) PCC2 PCC1 PCC0 XSEL MCM0 3 3 STOP X1 oscillation stabilization time counter Oscillation stabilization MOST MOST MOST MOST MOST time counter 11 13 14 15 16 status register (OSTC) High-speed system clock
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78K0/Kx2-L Internal bus Main clock mode register (MCM) Main OSC control register (MOC) Clock operation mode select register (OSCCTL) EXCLK OSCSEL MCS MSTOP OSTS2 OSTS1 OSTS0 Processor clock control register (PCC) Main clock mode register (MCM) Oscillation stabilization time select register (OSTS) XTSTART CLS XSEL MCM0 CSS PCC2 PCC1 PCC0 3 4 STOP X1 oscillation stabilization time counter Oscillation stabilization MOST MOST MOST MOST MOST time counter 11 13 14 15 16 status register (OSTC) High
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78K0/Kx2-L Remark CHAPTER 5 CLOCK GENERATOR fX: X1 clock oscillation frequency fIH: Internal high-speed oscillation clock frequency fEXCLK: External main system clock frequency fXH: High-speed system clock frequency fXP: Main system clock frequency fPRS: Peripheral hardware clock frequency fCPU: CPU clock frequency fXT: XT1 clock oscillation frequency fEXCLKS: External subsystem clock frequency fSUB: Subsystem clock frequency fIL: Internal low-speed oscillation clock frequency 5.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR Figure 5-3.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR Caution 3. The XT1 oscillator is a circuit with low amplification in order to achieve low-power consumption. Note the following points when designing the circuit. • Pins and circuit boards include parasitic capacitance. Therefore, perform oscillation evaluation using a circuit board to be actually used and confirm that there are no problems.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR Figure 5-6.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR Table 5-2. Relationship between CPU Clock and Minimum Instruction Execution Time CPU Clock (fCPU) Minimum Instruction Execution Time: 2/fCPU Note 2 Subsystem Clock Main System Clock Note 1 High-Speed System Note 1 Clock Internal High-Speed Oscillation Clock At 10 MHz Operation fXP At 8 MHz (TYP.) Operation At 4 MHz (TYP.) Operation At 32.768 kHz Operation 0.2 μs 0.25 μs (TYP.) 0.5 μs (TYP.) − 0.4 μs 0.5 μs (TYP.) 1.0 μs (TYP.) − fXP/2 2 0.8 μs 1.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR (4) Internal oscillation mode register (RCM) This register sets the operation mode of internal oscillator. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 80HNote 1. Figure 5-7.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR (5) Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU operates with a clock other than the high-speed system clock. MOC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 80H. Figure 5-8.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR (6) Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 5-9.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR (7) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock, the X1 clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR (8) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR Note (9) Peripheral enable register 0 (PER0) This register controls the clock supplied to peripheral functions other than the real-time counter. By stopping the clock supplied to such peripheral functions, the power consumption can be reduced. PER0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Note 78K0/KC2-L only Figure 5-12.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (1 to 10 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. Figure 5-13 shows an example of the external circuit of the X1 oscillator. Figure 5-13.
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78K0/Kx2-L Caution CHAPTER 5 CLOCK GENERATOR 1. When using the X1 oscillator and XT1 oscillator, wire as follows in the area enclosed by the broken lines in the Figures 5-13 and 5-14 to avoid an adverse effect from wiring capacitance. • Keep the wiring length as short as possible. • Do not cross the wiring with the other signal lines. Do not route the wiring near a signal line through which a high fluctuating current flows.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR Figure 5-15. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT VSS X1 X2 (c) Wiring near high alternating current VSS X1 X2 (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn X1 X2 High current VSS VSS A X1 B X2 C High current Remark When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR Figure 5-15. Examples of Incorrect Resonator Connection (2/2) (e) Signals are fetched VSS Remark X1 X2 When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. Caution 2. When X2 and XT1 are wired in parallel, the crosstalk noise of X2 may increase with XT1, resulting in malfunctioning. 5.4.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (refer to Figures 5-1 and 5-2).
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR Figure 5-16. Clock Generator Operation When Power Supply Voltage Is Turned On (When LVI Default Start Function Stopped Is Set (Option Byte: LVISTART = 0)) Power supply voltage (VDD) 1.8 V 1.61 V (TYP.) 0.5 V/ms (MIN.) 0V Internal reset signal <1> <3> Waiting for voltage stabilization (0.93 to 3.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR Cautions 1. If the voltage rises with a slope of less than 0.5 V/ms (MIN.) from power application until the voltage reaches 1.8 V, input a low level to the RESET pin from power application until the voltage reaches 1.8 V, or set the LVI default start function enabled by using the option byte (LVISTART = 1) (refer to Figure 5-17). When a low level has been input to the RESET pin until the voltage reaches 1.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR Notes 1. When releasing a reset (above figure) or releasing STOP mode while the CPU is operating on the internal high-speed oscillation clock, confirm the oscillation stabilization time for the X1 clock using the oscillation stabilization time counter status register (OSTC).
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR (1) Example of setting procedure when oscillating the X1 clock <1> Setting P121/X1 and P122/X2/EXCLK pins and selecting X1 clock or external clock (OSCCTL register) When EXCLK is cleared to 0 and OSCSEL is set to 1, the mode is switched from port mode to X1 oscillation mode.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR <2> Setting the high-speed system clock as the main system clock (MCM register) When XSEL and MCM0 are set to 1, the high-speed system clock is supplied as the main system clock and peripheral hardware clock.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR (b) To stop X1 oscillation (disabling external clock input) by setting MSTOP to 1 <1> Confirming the CPU clock status (PCC and MCM registers) Confirm with CLS and MCS that the CPU is operating on a clock other than the high-speed system clock. When CLS = 0 and MCS = 1, the high-speed system clock is supplied to the CPU, so change the CPU clock to a clock other than the high-speed system clock.
PAGE 238
78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR (2) Example of setting procedure when using internal high-speed oscillation clock as CPU clock, and internal high-speed oscillation clock or high-speed system clock as peripheral hardware clock <1> • Restarting oscillation of the internal high-speed oscillation clockNote (Refer to 5.6.2 (1) Example of setting procedure when restarting oscillation of the internal highspeed oscillation clock).
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR (3) Example of setting procedure when stopping the internal high-speed oscillation clock The internal high-speed oscillation clock can be stopped in the following two ways.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR 5.6.3 Example of controlling subsystem clock The following two types of subsystem clocksNote are available. • XT1 clock: Crystal/ceramic resonator is connected across the XT1 and XT2 pins. • External subsystem clock: External clock is input to the EXCLKS pin. When the subsystem clock is not used, the XT1/P123 and XT2/EXCLKS/P124 pins can be used as input port pins. Note 78K0/KC2-L only Cautions 1.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR (3) Example of setting procedure when using the subsystem clock as the CPU clock <1> Setting subsystem clock oscillationNote (Refer to 5.6.3 (1) Example of setting procedure when oscillating the XT1 clock and (2) Example of setting procedure when using the external subsystem clock.) Note The setting of <1> is not necessary when while the subsystem clock is operating.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR 5.6.4 Example of controlling internal low-speed oscillation clock The internal low-speed oscillation clock cannot be used as the CPU clock. Only the following peripheral hardware can operate with this clock. • Watchdog timer • 8-bit timer H1 (if fIL is selected as the count clock) In addition, the following operation modes can be selected by the option byte.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR 5.6.5 Clocks supplied to CPU and peripheral hardware The following table shows the relation among the clocks supplied to the CPU and peripheral hardware, and setting of registers. Table 5-4.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR 5.6.6 CPU clock status transition diagram Figures 5-18 and 5-19 show the CPU clock status transition diagram of this product. Figure 5-18. CPU Clock Status Transition Diagram (When LVI Default Start Mode Function Stopped Is Set (Option Byte: LVISTART = 0), 78K0/KY2-L, 78K0/KA2-L, and 78K0/KB2-L) Power ON Internal low-speed oscillation: Woken up Internal high-speed oscillation: Woken up X1 oscillation/EXCLK input: Stops (input port mode) VDD < 1.61 V (TYP.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR Figure 5-19. CPU Clock Status Transition Diagram (When LVI Default Start Mode Function Stopped Is Set (Option Byte: LVISTART = 0), 78K0/KC2-L) Internal low-speed oscillation: Woken up Internal high-speed oscillation: Woken up X1 oscillation/EXCLK input: Stops (input port mode) XT1 oscillation/EXCLKS input: Stops (input port mode) Power ON VDD < 1.61 V (TYP.) (A) VDD ≥ 1.61 V (TYP.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR Table 5-6 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-6. CPU Clock Transition and SFR Register Setting Examples (1/4) (1) CPU operating with internal high-speed oscillation clock (B) after reset release (A) Status Transition SFR Register Setting (A) → (B) SFR registers do not have to be set (default status after reset release).
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR Table 5-6.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR Table 5-6. CPU Clock Transition and SFR Register Setting Examples (3/4) (6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register RSTOP RSTS MCM0 0 Confirm this flag is 1.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR Table 5-6.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR 5.6.7 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 5-7.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR 5.6.8 Time required for switchover of CPU clock and main system clock By setting bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the CPU clock can be switched (between the main system clock and the subsystem clock) and the division ratio of the main system clock can be changed.
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78K0/Kx2-L Remark CHAPTER 5 CLOCK GENERATOR 2. When switching the CPU clock from the main system clock to the subsystem clock, calculate the number of clocks by rounding up to the next clock and discarding the decimal portion, as shown below. Example When switching CPU clock from fXP to fSUB (@ oscillation with fXP = 10 MHz, fSUB = 32.768 kHz) fXP/fSUB = 10000/32.768 ≅ 305.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR 5.6.9 Conditions before clock oscillation is stopped The following lists the register flag settings for stopping the clock oscillation (disabling external clock input) and conditions before the clock oscillation is stopped. Table 5-11.
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78K0/Kx2-L CHAPTER 5 CLOCK GENERATOR 5.6.10 Peripheral hardware and source clocks The following lists peripheral hardware and source clocks incorporated in the 78K0/Kx2-L microcontrollers. Remark The peripheral hardware depends on the product. Refer to 1.4 Block Diagram and 1.5 Outline of Functions. Table 5-13.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 78K0/KY2-L 78K0/KA2-L 78K0/KB2-L 78K0/KC2-L (μPD78F055x) (μPD78F056x) (μPD78F057x) (μPD78F058x) Item 16 Pins 20 Pins 25 Pins 32 Pins 30 Pins 40, 44, 48 Pins √ √ √ √ √ √ input: 1, output: 1 input: 1, output: 1 input: 1, input: 1 input: 1, output: 1 input: 1, output: 1 or or output: none or or or input: 2 input: 2 output 1 input: 2 input: 2 16-bit timer/event counter 00 Timer
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.2 Configuration of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 includes the following hardware. Table 6-1.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Cautions 1. The valid edge of TI010 and timer output (TO00) cannot be used for the P01 pin at the same time. Select either of the functions. 2. If clearing of bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) to 00 and input of the capture trigger conflict, then the captured data is undefined. 3.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) 16-bit timer capture/compare register 000 (CR000), 16-bit timer capture/compare register 010 (CR010) CR000 and CR010 are 16-bit registers that are used with a capture function or comparison function selected by using CRC00. Change the value of CR000 while the timer is stopped (TMC003 and TMC002 = 00). The value of CR010 can be changed during operation if the value has been set in a specific way. For details, refer to 6.5.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-4. Format of 16-Bit Timer Capture/Compare Register 010 (CR010) Address: FF14H, FF15H After reset: 0000H R/W FF15H 15 14 13 12 FF14H 11 10 9 8 7 6 5 4 3 2 1 0 CR010 (i) When CR010 is used as a compare register The value set in CR010 is constantly compared with the TM00 count value, and an interrupt request signal (INTTM010) is generated if they match.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Timer counter clear TM00 register Compare register set value (0000H) Operation Timer operation enable bit disabled (00) (TMC003, TMC002) Operation enabled (other than 00) Interrupt request signal Interrupt signal is not generated Interrupt signal is generated Remarks 1. N: CR000 register set value, M: CR010 register set value 2. For details of the operation enable bits (bits 3 and 2 (TMC003 and TMC002)), refer to 6.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Table 6-2.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.3 Registers Controlling 16-Bit Timer/Event Counter 00 Registers used to control 16-bit timer/event counter 00 are shown below.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FFBAH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 <0> TMC00 0 0 0 0 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 0 0 Operation enable of 16-bit timer/event counter 00 Disables 16-bit timer/event counter 00 operation. Stops supplying operating clock. Clears 16-bit timer counter 00 (TM00).
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-6.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) 16-bit timer output control register 00 (TOC00) TOC00 is an 8-bit register that controls the TO00 output. TOC00 can be rewritten while only OSPT00 is operating (when TMC003 and TMC002 = other than 00). Rewriting the other bits is prohibited during operation. However, TOC004 can be rewritten during timer operation as a means to rewrite CR010 (refer to 6.5.1 Rewriting CR010 during TM00 operation).
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-8. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H R/W Symbol 7 <6> <5> 4 <3> <2> 1 <0> TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger via software 0 − 1 One-shot pulse output The value of this bit is always “0” when it is read. Do not set this bit to 1 in a mode other than the oneshot pulse output mode.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) PRM00 is the register that sets the TM00 count clock and TI000 and TI010 pin input valid edges. Rewriting PRM00 is prohibited during operation (when TMC003 and TMC002 = other than 00). PRM00 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears PRM00 to 00H. Cautions 1.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-9.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (5) Port alternate switch control register (MUXSEL) (78K0/KA2-L (25-pin and 32-pin products) only) MUXSEL of 78K0/KA2-L (25-pin products) assigns TOH1, TI51, TI000, and INTP0 pins. y default, INTP0 and TI000 are assigned to P00, while TI51 and TOH1 have no assignment setting. MUXSEL of 78K0/KA2-L (32-pin products) assigns TOH1, TI000, and INTP0 pins. By default, INTP0 and TI000 and TOH1 have no assignment setting.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (6) Port mode register 0 (PM0) This register sets port 0 input/output in 1-bit units. When using the P01/TO00/TI010 pin for timer output, set PM01 and the output latches of P01 to 0. When using the P00/TI000 (P00/TI000/INTP0 in the 78K0/KY2-L and 78K0/KA2-L) and P01/TI010/TO00 pins for timer input, set PM00 and PM01 to 1. At this time, the output latches of P00 and P01 may be 0 or 1. PM0 can be set by a 1-bit or 8-bit memory manipulation instruction.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4 Operation of 16-Bit Timer/Event Counter 00 6.4.1 Interval timer operation If bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control register (TMC00) are set to 11 (clear & start mode entered upon a match between TM00 and CR000), the count operation is started in synchronization with the count clock. When the value of TM00 later matches the value of CR000, TM00 is cleared to 0000H and a match interrupt signal (INTTM000) is generated.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-14. Example of Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 1 1 0 OVF00 0 Clears and starts on match between TM00 and CR000.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-15. Example of Software Processing for Interval Timer Function N N N TM00 register 0000H Operable bits (TMC003, TMC002) 00 11 CR000 register N INTTM000 signal <1> <2> <1> Count operation start flow START Register initial setting PRM00 register, CRC00 register, CR000 register, port setting TMC003, TMC002 bits = 11 Initial setting of these registers is performed before setting the TMC003 and TMC002 bits to 11.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.2 Square-wave output operation When 16-bit timer/event counter 00 operates as an interval timer (refer to 6.4.1), a square wave can be output from the TO00 pin by setting the 16-bit timer output control register 00 (TOC00) to 03H. When TMC003 and TMC002 are set to 11 (count clear & start mode entered upon a match between TM00 and CR000), the counting operation is started in synchronization with the count clock.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-18. Example of Register Settings for Square-Wave Output Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 1 1 OVF00 0 0 Clears and starts on match between TM00 and CR000.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-19.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.3 External event counter operation When bits 1 and 0 (PRM001 and PRM000) of the prescaler mode register 00 (PRM00) are set to 11 (for counting up with the valid edge of the TI000 pin) and bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matching between TM00 and CR000 (INTTM000) is generated.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-21. Example of Register Settings in External Event Counter Mode (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 1 1 0 OVF00 0 Clears and starts on match between TM00 and CR000.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-21. Example of Register Settings in External Event Counter Mode (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) If M is set to CR000, the interrupt signal (INTTM000) is generated when the number of external events reaches (M + 1). Setting CR000 to 0000H is prohibited.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-22.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.4 Operation in clear & start mode entered by TI000 pin valid edge input When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 10 (clear & start mode entered by the TI000 pin valid edge input) and the count clock (set by PRM00) is supplied to the timer/event counter, TM00 starts counting up.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-24.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Operation in clear & start mode entered by TI000 pin valid edge input (CR000: compare register, CR010: capture register) Figure 6-25.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-26.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Operation in clear & start mode by entered TI000 pin valid edge input (CR000: capture register, CR010: compare register) Figure 6-27.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-28.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-28.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Operation in clear & start mode entered by TI000 pin valid edge input (CR000: capture register, CR010: capture register) Figure 6-29.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-30.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-30.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-31. Example of Register Settings in Clear & Start Mode Entered by TI000 Pin Valid Edge Input (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 1 0 OVF00 0/1 0 0: Inverts TO00 output on match between TM00 and CR000/CR010. 1: Inverts TO00 output on match between TM00 and CR000/CR010 and valid edge of TI000 pin. Clears and starts at valid edge input of TI000 pin.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-31.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-32.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.5 Free-running timer operation When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 01 (free-running timer mode), 16-bit timer/event counter 00 continues counting up in synchronization with the count clock. When it has counted up to FFFFH, the overflow flag (OVF00) is set to 1 at the next clock, and TM00 is cleared (to 0000H) and continues counting.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-34.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-36.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Free-running timer mode operation (CR000: capture register, CR010: capture register) Figure 6-37.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-38.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-38.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-39. Example of Register Settings in Free-Running Timer Mode (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 0 1 0/1 OVF00 0 0: Inverts TO00 output on match between TM00 and CR000/CR010. 1: Inverts TO00 output on match between TM00 and CR000/CR010 valid edge of TI000 pin.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-39.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-40.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.6 PPG output operation A square wave having a pulse width set in advance by CR010 is output from the TO00 pin as a PPG (Programmable Pulse Generator) signal during a cycle set by CR000 when bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 11 (clear & start upon a match between TM00 and CR000). The pulse cycle and duty factor of the pulse generated as the PPG output are as follows.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-42. Example of Register Settings for PPG Output Operation (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 1 1 0 OVF00 0 Clears and starts on match between TM00 and CR000.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-42. Example of Register Settings for PPG Output Operation (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) An interrupt signal (INTTM000) is generated when the value of this register matches the count value of TM00. The count value of TM00 is cleared.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-43.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.7 One-shot pulse output operation A one-shot pulse can be output by setting bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control register 00 (TMC00) to 01 (free-running timer mode) or to 10 (clear & start mode entered by the TI000 pin valid edge) and setting bit 5 (OSPE00) of 16-bit timer output control register 00 (TOC00) to 1.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-45. Example of Register Settings for One-Shot Pulse Output Operation (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 0/1 0/1 0 OVF00 0 01: Free running timer mode 10: Clear and start mode by valid edge of TI000 pin.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-45. Example of Register Settings for One-Shot Pulse Output Operation (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) This register is used as a compare register when a one-shot pulse is output. When the value of TM00 matches that of CR000, an interrupt signal (INTTM000) is generated and the TO00 output level is inverted.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-46.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-46. Example of Software Processing for One-Shot Pulse Output Operation (2/2) <1> Count operation start flow START Register initial setting PRM00 register, CRC00 register, TOC00 registerNote, CR000, CR010 registers, port setting TMC003, TMC002 bits = 01 or 10 Initial setting of these registers is performed before setting the TMC003 and TMC002 bits. Starts count operation <2> One-shot trigger input flow TOC00.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.8 Pulse width measurement operation TM00 can be used to measure the pulse width of the signal input to the TI000 and TI010 pins. Measurement can be accomplished by operating the 16-bit timer/event counter 00 in the free-running timer mode or by restarting the timer in synchronization with the signal input to the TI000 pin. When an interrupt is generated, read the value of the valid capture register and measure the pulse width.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 A pulse width can be measured in the following three ways. • Measuring the pulse width by using two input signals of the TI000 and TI010 pins (free-running timer mode) • Measuring the pulse width by using one input signal of the TI000 pin (free-running timer mode) • Measuring the pulse width by using one input signal of the TI000 pin (clear & start mode entered by the TI000 pin valid edge input) Remarks 1. For the setting of the I/O pins, refer to 6.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Measuring the pulse width by using one input signal of the TI000 pin (free-running timer mode) Set the free-running timer mode (TMC003 and TMC002 = 01). The count value of TM00 is captured to CR000 in the phase reverse to the valid edge detected on the TI000 pin. When the valid edge of the TI000 pin is detected, the count value of TM00 is captured to CR010.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Measuring the pulse width by using one input signal of the TI000 pin (clear & start mode entered by the TI000 pin valid edge input) Set the clear & start mode entered by the TI000 pin valid edge (TMC003 and TMC002 = 10). The count value of TM00 is captured to CR000 in the phase reverse to the valid edge of the TI000 pin, and the count value of TM00 is captured to CR010 and TM00 is cleared (0000H) when the valid edge of the TI000 pin is detected.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-52. Example of Register Settings for Pulse Width Measurement (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 0/1 0/1 0 OVF00 0 01: Free running timer mode 10: Clear and start mode entered by valid edge of TI000 pin. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 0 0 0 0 0 1 0/1 1 1: CR000 used as capture register 0: TI010 pin is used as capture trigger of CR000.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-52. Example of Register Settings for Pulse Width Measurement (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) This register is used as a capture register. Either the TI000 or TI010 pin is selected as a capture trigger. When a specified edge of the capture trigger is detected, the count value of TM00 is stored in CR000.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-53.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-53. Example of Software Processing for Pulse Width Measurement (2/2) <1> Count operation start flow START Register initial setting PRM00 register, CRC00 register, port setting TMC003, TMC002 bits = 01 or 10 Initial setting of these registers is performed before setting the TMC003 and TMC002 bits.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.5 Special Use of TM00 6.5.1 Rewriting CR010 during TM00 operation In principle, rewriting CR000 and CR010 of the 78K0/Kx2-L microcontrollers when they are used as compare registers is prohibited while TM00 is operating (TMC003 and TMC002 = other than 00). However, the value of CR010 can be changed, even while TM00 is operating, using the following procedure if CR010 is used for PPG output and the duty factor is changed.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Setting LVS00 and LVR00 Set LVS00 and LVR00 using the following procedure. Figure 6-54. Example of Flow for Setting LVS00 and LVR00 Bits Setting TOC00.OSPE00, TOC004, TOC001 bits <1> Setting of timer output operation Setting TOC00.TOE00 bit Setting TOC00.LVS00, LVR00 bits Setting TMC00.TMC003, TMC002 bits <2> Setting of timer output F/F <3> Enabling timer operation Caution Be sure to set LVS00 and LVR00 following steps <1>, <2>, and <3> above.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.6 Cautions for 16-Bit Timer/Event Counter 00 (1) Restrictions for each channel of 16-bit timer/event counter 00 Table 6-3 shows the restrictions for each channel. Table 6-3.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Timing of holding data by capture register (a) When the valid edge is input to the TI000/TI010 pin and the reverse phase of the TI000 pin is detected while CR000/CR010 is read, CR010 performs a capture operation but the read value of CR000/CR010 is not guaranteed.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (7) Operation of OVF00 flag (a) Setting OVF00 flag (1) The OVF00 flag is set to 1 in the following case, as well as when TM00 overflows. Select the clear & start mode entered upon a match between TM00 and CR000. ↓ Set CR000 to FFFFH. ↓ When TM00 matches CR000 and TM00 is cleared from FFFFH to 0000H Figure 6-58.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (9) Capture operation (a) When valid edge of TI000 is specified as count clock When the valid edge of TI000 is specified as the count clock, the capture register for which TI000 is specified as a trigger does not operate correctly.
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78K0/Kx2-L CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (12) Reading of 16-bit timer counter 00 (TM00) TM00 can be read without stopping the actual counter, because the count values captured to the buffer are fixed when it is read. The buffer, however, may not be updated when it is read immediately before the counter counts up, because the buffer is updated at the timing the counter counts up. Figure 6-59.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 78K0/KY2-L 78K0/KA2-L 78K0/KB2-L 78K0/KC2-L (μPD78F055x) (μPD78F056x) (μPD78F057x) (μPD78F058x) 30 Pins 40, 44, 48 Pins Item 16 Pins 20 Pins 25 Pins 32 Pins − − − − √ (PWM output: 1) √ (No output) √ (No output) √ √ (No I/O) √ (PWM output: 1) 8-bit timer/event counter 50 8-bit timer/event counter 51 (No output Note ) Remark √: Mounted, −: Not mounted Note When bits 3
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.2 Configuration of 8-Bit Timer/Event Counters 50 and 51 8-bit timer/event counters 50 and 51 include the following hardware. Table 7-1.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-1.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-3.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) 8-bit timer counter 5n (TM5n) TM5n is an 8-bit register that counts the count pulses and is read-only. The counter is incremented in synchronization with the rising edge of the count clock. Figure 7-5. Format of 8-Bit Timer Counter 5n (TM5n) Address: FF16H (TM50), FF1FH (TM51) After reset: 00H R Symbol TM5n In the following situations, the count value is cleared to 00H.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.3 Registers Controlling 8-Bit Timer/Event Counters 50 and 51 The following five registers are used to control 8-bit timer/event counters 50 and 51.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-8. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 TCL51 0 0 0 0 0 TCL512 TCL511 TCL510 TCL512 TCL511 TCL510 Note 1 Count clock selection fPRS = 2 MHz 0 0 0 TI51 pin falling edge 0 0 1 TI51 pin rising edge 0 1 0 fPRS 0 1 1 fPRS/2 1 1 Notes 1. 0 0 0 1 fPRS = 5 MHz fPRS = 10 MHz Note 2 Note 2 2 MHz 5 MHz 10 MHz 1 MHz 2.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that performs the following five types of settings. <1> 8-bit timer counter 5n (TM5n) count operation control <2> 8-bit timer counter 5n (TM5n) operating mode selection <3> Timer output F/F (flip flop) status setting <4> Active level selection in timer F/F control or PWM (free-running) mode.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-9.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-10. Format of 8-Bit Timer Mode Control Register 51 (TMC51) (1/2) (a) 78K0/KY2-L, 78K0/KA2-L Address: FF43H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 0 TMC51 TCE51 0 0 0 0 0 0 0 TCE51 TM51 count operation control 0 After clearing to 0, count operation disabled (counter stopped) 1 Count operation start R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-10.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (3) Port alternate switch control register (MUXSEL) (78K0/KA2-L (25-pin) only) MUXSEL of 78K0/KA2-L (25-pin products) assigns TOH1, TI51, TI000, and INTP0 pins. By default, INTP0 and TI000 are assigned to P00, while TI51 and TOH1 have no assignment setting. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears MUXSEL to 00H. Figure 7-11.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-12. Format of Port Mode Register 0 (PM0) Address: FF20H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM0 1 1 1 1 1 PM02 PM01 PM00 PM0n P0n pin I/O mode selection (n = 0 to 2) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Remark The figure shown above presents the format of port mode register 0 of the 78K0/KA2-L (25-pin products). Figure 7-13.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4 Operations of 8-Bit Timer/Event Counters 50 and 51 7.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n).
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-15. Interval Timer Operation Timing (2/2) (b) When CR5n = 00H t Count clock TM5n 00H 00H 00H CR5n 00H 00H TCE5n INTTM5n Interval time (c) When CR5n = FFH t Count clock TM5n CR5n 01H FFH FEH FFH 00H FEH FFH FFH 00H FFH TCE5n INTTM5n Interrupt acknowledged Interrupt acknowledged Interval time Remark 78K0/KY2-L, 78K0/KA2-L: n = 1 78K0/KB2-L, 78K0/KC2-L: n = 0, 1 R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.2 Operation as external event counter The external event counter counts the number of external clock pulses to be input to the TI5n pin by 8-bit timer counter 5n (TM5n). TM5n is incremented each time the valid edge specified by timer clock selection register 5n (TCL5n) is input. Either the rising or falling edge can be selected.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.4.3 Square-wave output operation A square wave with any selected frequency is output at intervals determined by the value preset to 8-bit timer compare register 5n (CR5n). The TO5n pin output status is inverted at intervals determined by the count value preset to CR5n by setting bit 0 (TOE5n) of 8-bit timer mode control register 5n (TMC5n) to 1. This enables a square wave with any selected frequency to be output (duty = 50%).
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-17. Square-Wave Output Operation Timing t Count clock TM5n count value 00H 01H 02H N−1 N 00H 01H 02H N−1 N 00H Count start CR5n N TO5nNote Note The initial value of TO5n output can be set by bits 2 and 3 (LVR5n, LVS5n) of 8-bit timer mode control register 5n (TMC5n). 7.4.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (1) PWM output basic operation Setting <1> Set each register. • Clear the port output latch (P17 or P33)Note and port mode register (PM17 or PM33)Note to 0. • TCL5n: Select the count clock. • CR5n: Compare value • TMC5n: Stop the count operation, select PWM mode. The timer output F/F is not changed.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 Figure 7-18.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 (2) Operation with CR5n changed Figure 7-19. Timing of Operation with CR5n Changed (a) CR5n value is changed from N to M before clock rising edge of FFH → Value is transferred to CR5n at overflow immediately after change.
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78K0/Kx2-L CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50 AND 51 7.5 Cautions for 8-Bit Timer/Event Counters 50 and 51 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50 and 51 (TM50, TM51) are started asynchronously to the count clock. Figure 7-20.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 CHAPTER 8 8-BIT TIMERS H0 AND H1 78K0/KY2-L 78K0/KA2-L 78K0/KB2-L 78K0/KC2-L (μPD78F055x) (μPD78F056x) (μPD78F057x) (μPD78F058x) 30 Pins 40, 44, 48 Pins Item 16 Pins 20 Pins 25, 32 Pins √ (PWM output: 1) − 8-bit timer H0 √ (PWM output: 1) 8-bit timer H1 √ (PWM output: 1) √ Note (PWM output: 1 ) Remark √: Mounted, −: Not mounted Note Only when the TOH1 function is assigned by setting the MUXSEL register 8.
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78K0/Kx2-L R01UH0028EJ0400 Rev.4.00 Sep 27, 2010 Figure 8-1.
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78K0/Kx2-L R01UH0028EJ0400 Rev.4.00 Sep 27, 2010 Figure 8-2.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 (1) 8-bit timer H compare register 0n (CMP0n) This register can be read or written by an 8-bit memory manipulation instruction. This register is used in all of the timer operation modes. This register constantly compares the value set to CMP0n with the count value of the 8-bit timer counter Hn and, when the two values match, generates an interrupt request signal (INTTMHn) and inverts the output level of TOHn.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 8.3 Registers Controlling 8-Bit Timers H0 and H1 The following five registers are used to control 8-bit timers H0 and H1.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-5.
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78K0/Kx2-L Note 2. CHAPTER 8 8-BIT TIMERS H0 AND H1 Note the following points when selecting the TM50 output as the count clock. • Mode in which the count clock is cleared and started upon a match of TM50 and CR50 (TMC506 = 0) Start the operation of 8-bit timer/event counter 50 first and then enable the timer F/F inversion operation (TMC501 = 1). • PWM mode (TMC506 = 1) Start the operation of 8-bit timer/event counter 50 first and then set the count clock to make the duty = 50%.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-6.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 Cautions 1. When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited. However, TMHMD1 can be refreshed (the same value is written). 2. In the PWM output mode and carrier generator mode, be sure to set the 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11). 3.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 (3) Port alternate switch control register (MUXSEL) (78K0/KA2-L (25, 32-pin products) only) MUXSEL of 78K0/KA2-L (25-pin and 32-pin products) assigns TOH1, TI51, TI000, and INTP0 pins. By default, TOH1 has no assignment setting. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears MUXSEL to 00H. Figure 8-8.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 (4) Port mode register 0 (PM0), port mode register 1 (PM1), port mode register 3 (PM3) This register sets port 0 input/output, port 1 input/output, and port 3 input/output in 1-bit units. • 78K0/KY2-L, 78K0/KA2-L (20-pin products) When using the P30/TOH1/TI51/INTP1 pins for timer output, clear PM30 and the output latches of P30 to 0.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-11. Format of Port Mode Register 3 (PM3) Address: FF23H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM3 1 1 1 1 1 PM32 PM31 PM30 PM3n P3n pin I/O mode selection (n = 0 to 2) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Remark The figure shown above presents the format of port mode register 3 of the 78K0/KA2-L (20-pin products).
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4 Operation of 8-Bit Timers H0 and H1 8.4.1 Operation as interval timer/square-wave output When the 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and the 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-13.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-13.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4.2 Operation as PWM output In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. The 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited. The 8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n register during timer operation is possible.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained. <6> To stop the count operation, set TMHEn = 0. If the setting value of the CMP0n register is N, the setting value of the CMP1n register is M, and the count clock frequency is fCNT, the PWM pulse output cycle and duty are as follows. • PWM pulse output cycle = (N + 1)/fCNT • Duty = (M + 1)/(N + 1) Cautions 1.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15. Operation Timing in PWM Output Mode (1/4) (a) Basic operation Count clock 8-bit timer counter Hn 00H 01H A5H 00H 01H 02H CMP0n A5H CMP1n 01H A5H 00H 01H 02H A5H 00H TMHEn INTTMHn TOHn (TOLEVn = 0) <1> <2> <3> <4> TOHn (TOLEVn = 1) <1> The count operation is enabled by setting the TMHEn bit to 1. Start the 8-bit timer counter Hn by masking one count clock to count up. At this time, PWM output outputs an inactive level.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15. Operation Timing in PWM Output Mode (3/4) (d) Operation when CMP0n = 01H, CMP1n = 00H Count clock 8-bit timer counter Hn 00H 01H 00H 01H 00H 00H 01H 00H 01H CMP0n 01H CMP1n 00H TMHEn INTTMHn TOHn (TOLEVn = 0) Remark 78K0/KY2-L, 78K0/KA2-L: n = 1 78K0/KB2-L, 78K0/KC2-L: n = 0, 1 R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-15. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 02H → 03H, CMP0n = A5H) Count clock 8-bit timer counter Hn 00H 01H 02H 80H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H A5H CMP01 02H (03H) 02H CMP11 <2> 03H <2>’ TMHE1 INTTMH1 TOH1 (TOLEV1 = 0) <1> <3> <4> <5> <6> <1> The count operation is enabled by setting TMHEn = 1. Start the 8-bit timer counter Hn by masking one count clock to count up.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 8.4.3 Carrier generator operation (8-bit timer H1 only) In the carrier generator mode, the 8-bit timer H1 is used to generate the carrier signal of an infrared remote controller, and the 8-bit timer/event counter 51 is used to generate an infrared remote control signal (time count). The carrier clock generated by the 8-bit timer H1 is output in the cycle set by the 8-bit timer/event counter 51.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal. The INTTM5H1 signal becomes the data transfer signal of the NRZ1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 Setting <1> Set each register. Figure 8-17.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 <10> By performing the procedures above, an arbitrary carrier clock is obtained. To stop the count operation, clear TMHE1 to 0. If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is fCNT, the carrier clock output cycle and duty are as follows. • Carrier clock output cycle = (N + M + 2)/fCNT • Duty = High-level width/carrier clock output width = (M + 1)/(N + M + 2) Cautions 1.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-18.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-18.
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78K0/Kx2-L CHAPTER 8 8-BIT TIMERS H0 AND H1 Figure 8-18. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter H1 count value 00H 01H N 00H 01H M 00H N 00H 01H L 00H N CMP01 <3> M CMP11 <3>’ M (L) L TMHE1 INTTMH1 <2> Carrier clock <4> <5> <1> <1> When TMHE1 = 1 is set, the 8-bit timer H1 starts a count operation. At that time, the carrier clock remains default.
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78K0/Kx2-L CHAPTER 9 WATCHDOG TIMER CHAPTER 9 WATCHDOG TIMER 9.1 Functions of Watchdog Timer The watchdog timer is mounted onto all 78K0/Kx2-L microcontroller products. The watchdog timer operates on the internal low-speed oscillation clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. Program loop is detected in the following cases.
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78K0/Kx2-L CHAPTER 9 WATCHDOG TIMER 9.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 9-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, and window open period are set by the option byte. Table 9-2.
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78K0/Kx2-L CHAPTER 9 WATCHDOG TIMER 9.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). (1) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 9AH or 1AHNote. Figure 9-2.
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78K0/Kx2-L CHAPTER 9 WATCHDOG TIMER 9.4 Operation of Watchdog Timer 9.4.1 Controlling operation of watchdog timer 1. When the watchdog timer is used, its operation is specified by the option byte (0080H). • Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1 (the counter starts operating after a reset release) (for details, refer to CHAPTER 24).
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78K0/Kx2-L CHAPTER 9 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (LSROSC) of the option byte. LSROSC = 0 (Internal Low-Speed LSROSC = 1 (Internal Low-Speed Oscillator Can Be Stopped by Software) Oscillator Cannot Be Stopped) Watchdog timer operation stops. In HALT mode Watchdog timer operation continues.
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78K0/Kx2-L CHAPTER 9 WATCHDOG TIMER 9.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (0080H). The outline of the window is as follows. • If “ACH” is written to WDTE during the window open period, the watchdog timer is cleared and starts counting again. • Even if “ACH” is written to WDTE during the window close period, an abnormality is detected and an internal reset signal is generated.
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78K0/Kx2-L CHAPTER 9 WATCHDOG TIMER 17 Remark If the overflow time is set to 2 /fIL, the window close time and open time are as follows. Setting of Window Open Period 25% 50% 75% 100% Window close time 0 to 3.64 s 0 to 2.43 s 0 to 1.21 s None Window open time 3.64 to 3.97 s 2.43 to 3.97 s 1.21 to 3.97 s 0 to 3.97 s • Overflow time: 217/fIL (MAX.) = 217/33 kHz (MAX.) = 3.97 s • Window close time: 0 to 217/fIL (MIN.) × (1 − 0.25) = 0 to 217/27 kHz (MIN.) × 0.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER CHAPTER 10 REAL-TIME COUNTER Item 78K0/KY2-L 78K0/KA2-L 78K0/KB2-L 78K0/KC2-L (μPD78F055x) (μPD78F056x) (μPD78F057x) (μPD78F058x) 16 Pins 20, 25, 32 Pins 30 Pins 40 Pins √ (RTC − Real-time counter 44 Pins 48 Pins √ (RTC output: 2) output: none) Remark √: Mounted, −: Not mounted 10.1 Functions of Real-Time Counter The real-time counter has the following features.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER Figure 10-1.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER 10.3 Registers Controlling Real-Time Counter The real-time counter is controlled by the following 18 registers.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER (1) Peripheral enable register 0 (PER0) This register controls the clock supplied to peripheral functions other than the real-time counter. By stopping the clock supplied to such peripheral functions, the power consumption can be reduced. PER0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 10-2.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER Figure 10-3. Format of Real-Time Counter Control Register 0 (RTCC0) Address: FF9DH After reset: 00H R/W Symbol <7> 6 <5> <4> 3 2 1 0 RTCC0 RTCE 0 RCLOE1 RCLOE0 AMPM CT2 CT1 CT0 RTCE Real-time counter operation control 0 Stops counter operation. 1 Starts counter operation. RCLOE1 Note 1 RTC1HZ pin output control 0 Disables output of RTC1HZ pin (1 Hz). 1 Enables output of RTC1HZ pin (1 Hz).
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER (3) Real-time counter control register 1 (RTCC1) The RTCC1 register is an 8-bit register that is used to control the alarm interrupt function and the wait time of the counter. RTCC1 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 10-4.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER Figure 10-4. Format of Real-Time Counter Control Register 1 (RTCC1) (2/2) RIFG Constant-period interrupt status flag 0 Constant-period interrupt is not generated. 1 Constant-period interrupt is generated. This flag indicates the status of generation of the constant-period interrupt. When the constant-period interrupt is generated, it is set to “1”. This flag is cleared when “0” is written to it. Writing “1” to it is invalid.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER (4) Real-time counter control register 2 (RTCC2) The RTCC2 register is an 8-bit register that is used to control the interval interrupt function and the RTCDIV pin. RTCC2 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 10-5.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER (5) Sub-count register (RSUBC) The RSUBC register is a 16-bit register that counts the reference time of 1 second of the real-time counter. It takes a value of 0000H to 7FFFH and counts 1 second with a clock of 32.768 kHz. RSUBC can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Cautions 1. When a correction is made by using the SUBCUD register, the value may become 8000H or more. 2.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER (7) Minute count register (MIN) The MIN register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of minutes. It counts up when the second counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER Table 10-2. Displayed Time Digits 24-Hour Display (AMPM bit = 1) 12-Hour Display (AMPM bit = 0) Time HOUR Register Time HOUR Register 0 00H 0 a.m. 12H 1 01H 1 a.m. 01H 2 02H 2 a.m. 02H 3 03H 3 a.m. 03H 4 04H 4 a.m. 04H 5 05H 5 a.m. 05H 6 06H 6 a.m. 06H 7 07H 7 a.m. 07H 8 08H 8 a.m. 08H 9 09H 9 a.m. 09H 10 10H 10 a.m. 10H 11 11H 11 a.m. 11H 12 12H 0 p.m. 32H 13 13H 1 p.m. 21H 14 14H 2 p.m.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER Figure 10-10. Format of Day Count Register (DAY) Address: FFB6H After reset: 01H R/W Symbol 7 6 5 4 3 2 1 0 DAY 0 0 DAY20 DAY10 DAY8 DAY4 DAY2 DAY1 (10) Week count register (WEEK) The WEEK register is an 8-bit register that takes a value of 0 to 6 (decimal) and indicates the count value of weekdays. It counts up in synchronization with the day counter.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER (11) Month count register (MONTH) The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of months. It counts up when the day counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later. Even if the day count register overflows while this register is being written, this register ignores the overflow and is set to the value written.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER (13) Watch error correction register (SUBCUD) This register is used to correct the watch with high accuracy when it is slow or fast by changing the value that overflows from the sub-count register (RSUBC) to the second count register (reference value: 7FFFH). SUBCUD can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 10-14.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER (14) Alarm minute register (ALARMWM) This register is used to set minutes of alarm. ALARMWM can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Caution Set a decimal value of 00 to 59 to this register in BCD code. If a value outside the range is set, the alarm is not detected. Figure 10-15.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER Here is an example of setting the alarm. Time of Alarm Day 12-Hour Display Sunday Monday Tuesday Wednesday Thursday Friday Saturday Hour Hour 24-Hour Display Hour Hour 10 1 Minute Minute 10 1 10 1 Minute Minute 10 1 W W W W W W W W W W W W W W 0 1 2 3 4 5 6 Every day, 0:00 a.m. 1 1 1 1 1 1 1 1 2 0 0 0 0 0 0 Every day, 1:30 a.m. 1 1 1 1 1 1 1 0 1 3 0 0 1 3 0 Every day, 11:59 a.m.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER 10.4 Real-Time Counter Operation 10.4.1 Starting operation of real-time counter Figure 10-19. Procedure for Starting Operation of Real-Time Counter Start RTCEN = 1Note 1 RTCE = 0 Setting AMPM, CT2 to CT0 Supplies input clock. Stops counter operation. Selects 12-/24-hour system and interrupt (INTRTC). Setting SEC (clearing RSUBC) Sets second count register. Setting MIN Sets minute count register. Setting HOUR Sets hour count register.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER 10.4.2 Shifting to STOP mode after starting operation Perform one of the following processing when shifting to STOP mode immediately after setting RTCE to 1. However, after setting RTCE to 1, this processing is not required when shifting to STOP mode after the first INTRTC interrupt has occurred. • Shifting to STOP mode when at least two subsystem clocks (fSUB) (about 62 μ s) have elapsed after setting RTCE to 1 (see Figure 10-20, Example 1).
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER 10.4.3 Reading/writing real-time counter Read or write the counter after setting 1 to RWAIT first. Figure 10-21. Procedure for Reading Real-Time Counter Start No RWAIT = 1 Stops SEC to YEAR counters. Mode to read and write count values RWST = 1? Checks wait status of counter. Yes Reading SEC Reads second count register. Reading MIN Reads minute count register. Reading HOUR Reads hour count register. Reading WEEK Reads week count register.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER Figure 10-22. Procedure for Writing Real-Time Counter Start No RWAIT = 1 Stops SEC to YEAR counters. Mode to read and write count values RWST = 1? Checks wait status of counter. Yes Writing SEC Writes second count register. Writing MIN Writes minute count register. Writing HOUR Writes hour count register. Writing WEEK Writes week count register. Writing DAY Writing MONTH No Writes day count register. Writes month count register.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER 10.4.4 Setting alarm of real-time counter Set time of alarm after setting 0 to WALE first. Figure 10-23. Alarm Setting Procedure Start WALE = 0 Match operation of alarm is invalid. WALIE = 1 Interrupt is generated when alarm matches. Setting ALARMWM Sets alarm minute register. Setting ALARMWH Sets alarm hour register. Setting ALARMWW Sets alarm week register. WALE = 1 No Match operation of alarm is valid.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER 10.4.5 1 Hz output of real-time counter Set 1 Hz output after setting 0 to RTCE first. Figure 10-24. 1 Hz Output Setting Procedure Start RTCE = 0 RCLOE1 = 1 RTCE = 1 Stops counter operation. Enables output of RTC1HZ pin (1 Hz). Starts counter operation. Output start from RTC1HZ pin 10.4.6 32.768 kHz output of real-time counter Set 32.768 kHz output after setting 0 to RTCE first. Figure 10-25. 32.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER 10.4.7 512 Hz, 16.384 kHz output of real-time counter Set 512 Hz or 16.384 kHz output after setting 0 to RTCE first. Figure 10-26. 512 Hz, 16.384 kHz output Setting Procedure Start RTCE = 0 512 Hz Output: RCKDIV = 0 16.384 kHz Output: RCKDIV = 1 RCLOE2 = 1 RTCE = 1 Stops counter operation. Selects output frequency of RTCDIV pin. Output of RTCDIV pin is enabled. Starts counter operation. 512 Hz or 16.384 kHz output start from RTCDIV pin R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER 10.4.8 Example of watch error correction of real-time counter The watch can be corrected with high accuracy when it is slow or fast, by setting a value to the watch error correction register. Example of calculating the correction value The correction value used when correcting the count value of the sub-count register (RSUBC) is calculated by using the following expression. Set DEV to 0 when the correction range is −63.1 ppm or less, or 63.1 ppm or more.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER Correction example <1> Example of correcting from 32772.3 Hz to 32768 Hz (32772.3 Hz − 131.2 ppm) [Measuring the oscillation frequency] The oscillation frequencyNote of each product is measured by outputting about 32 kHz from the RTCCL pin or outputting about 1 Hz from the RTC1HZ pin when the watch error correction register is set to its initial value (00H). Note Refer to 10.4.
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78K0/Kx2-L R01UH0028EJ0400 Rev.4.00 Sep 27, 2010 Figure 10-27.
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78K0/Kx2-L CHAPTER 10 REAL-TIME COUNTER Correction example <2> Example of correcting from 32767.4 Hz to 32768 Hz (32767.4 Hz + 18.3 ppm) [Measuring the oscillation frequency] The oscillation frequencyNote of each product is measured by outputting about 32 kHz from the RTCCL pin or outputting about 1 Hz from the RTC1HZ pin when the watch error correction register is set to its initial value (00H). Note Refer to 10.4.
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78K0/Kx2-L R01UH0028EJ0400 Rev.4.00 Sep 27, 2010 Figure 10-28.
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78K0/Kx2-L CHAPTER 11 CLOCK OUTPUT CONTROLLER CHAPTER 11 CLOCK OUTPUT CONTROLLER Item 78K0/KY2-L 78K0/KA2-L 78K0/KB2-L 78K0/KC2-L (μPD78F055x) (μPD78F056x) (μPD78F057x) (μPD78F058x) 16 Pins 20, 25, 32 Pins 30 Pins 40, 44 Pins − Clock output 48 Pins √ controller Remark √: Mounted, −: Not mounted 11.1 Functions of Clock Output Controller The clock output controller is intended for carrier output during remote controlled transmission and clock output for supply to peripheral ICs.
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78K0/Kx2-L CHAPTER 11 CLOCK OUTPUT CONTROLLER 11.3 Registers Controlling Clock Output Controller The following two registers are used to control the clock output controller. • Clock output selection register (CKS) • Port mode register 4 (PM4) (1) Clock output selection register (CKS) This register sets output enable/disable for clock output (PCL) and sets the output clock. CKS is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears CKS to 00H. Figure 11-2.
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78K0/Kx2-L CHAPTER 11 CLOCK OUTPUT CONTROLLER Remarks 1. fPRS: Peripheral hardware clock frequency 2. fSUB: Subsystem clock frequency (2) Port mode register 4 (PM4) This register sets port 4 input/output in 1-bit units. When using the P42/PCL/SSI11/INTP6 pin for clock output, clear PM42 and the output latches of P42 to 0. PM4 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM4 to FFH. Figure 11-3.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER CHAPTER 12 A/D CONVERTER Item 78K0/KY2-L 78K0/KA2-L 78K0/KB2-L 78K0/KC2-L (μPD78F055x) (μPD78F056x) (μPD78F057x) (μPD78F058x) 16 Pins 10-bit A/D 4 ch 20 Pins 6 ch 25 Pins 7 ch 32 Pins 11 ch 30 Pins 7 ch 40 Pins 10 ch 44 Pins 11 ch 48 Pins 11 ch converter 12.1 Function of A/D Converter The A/D converter converts an analog input signal into a digital value, and consists of up to 11 channels (ANI0 to ANI10) with a resolution of 10 bits.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER Figure 12-1.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER 12.2 Configuration of A/D Converter The A/D converter includes the following hardware. (1) ANI0 to ANI10 pins These are the analog input pins of the 11-channel A/D converter. They input analog signals to be converted into digital signals. Pins other than the one selected as the analog input pin can be used as I/O port pins. Remark A/D converter analog input pins differ depending on products.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER (8) Successive approximation register (SAR) The SAR register is a 10-bit register that sets a result compared by the A/D voltage comparator, 1 bit at a time starting from the most significant bit (MSB). If data is set in the SAR register all the way to the least significant bit (LSB) (end of A/D conversion), the contents of the SAR register (conversion results) are held in the A/D conversion result register (ADCR, ADCRH).
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER 12.3 Registers Used in A/D Converter The A/D converter uses the following seven registers.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER Figure 12-3. Timing Chart When Comparator Is Used Comparator operation ADCE A/D voltage comparator Conversion operation Conversion waiting Conversion operation Conversion stopped ADCS Note 1 LV0 (set to low-voltage mode or high-speed mode) Note 2 Notes 1. To stabilize the internal circuit, the time from setting ADCE to 1 to setting ADCS to 1 must be 1 μs or longer. 2.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER Table 12-2. A/D Conversion Time Selection (1/3) (1) 4.0 V ≤ AVREF ≤ 5.5 V A/D Converter Mode Register 0 Conversion Time Selection Mode Conversion (ADM0) Clock (fAD) FR2 FR1 FR0 LV1 LV0 0 0 0 0 0 0 0 0 0 fPRS = 4 MHz fPRS = 8 MHz fPRS = 10 MHz 264/fPRS 66.0 μs 33.0 μs 26.4 μs fPRS/12 1 176/fPRS 44.0 μs 22.0 μs 17.6 μs fPRS/8 1 0 132/fPRS 33.0 μs 16.5 μs 13.2 μs fPRS/6 1 1 88/fPRS 22.0 μs 11.0 μs 8.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER Table 12-2. A/D Conversion Time Selection (2/3) (2) 2.7 V ≤ AVREF < 4.0 V A/D Converter Mode Register 0 Conversion Time Selection Mode Conversion (ADM0) Clock (fAD) FR2 FR1 FR0 LV1 LV0 0 0 0 0 0 0 0 0 0 fPRS = 4 MHz fPRS = 8 MHz fPRS = 10 MHz 264/fPRS 66.0 μs 33.0 μs 26.4 μs fPRS/12 1 176/fPRS 44.0 μs 22.0 μs 17.6 μs fPRS/8 1 0 132/fPRS 33.0 μs 16.5 μs 13.2 μs 1 1 88/fPRS 22.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER Table 12-2. A/D Conversion Time Selection (3/3) (3) 1.8 V ≤ AVREF < 2.7 V A/D Converter Mode Register 0 Conversion Time Selection Mode Conversion (ADM0) Clock (fAD) FR2 FR1 FR0 LV1 LV0 0 0 0 0 1 fPRS = 4 MHz Low-voltage 528/fPRS Setting fPRS = 8 MHz fPRS = 10 MHz 66.0 μs 52.8 μs fPRS/12 44.0 μs Setting fPRS/8 prohibited 0 0 1 352/fPRS Setting prohibited prohibited 0 1 0 264/fPRS 66.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER Figure 12-4. A/D Converter Sampling and A/D Conversion Timing ADCS ← 1 or ADS rewrite ADCS Sampling timing INTAD SAR clear Wait periodNote Sampling Sampling Successive conversion Transfer SAR to ADCR, clear INTAD generation Conversion time Conversion time Note For details of wait period, refer to CHAPTER 31 CAUTIONS FOR WAIT. (2) 10-bit A/D conversion result register (ADCR) This register is a 16-bit register that stores the A/D conversion result.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER (3) 8-bit A/D conversion result register L (ADCRL) This register is an 8-bit register that stores the A/D conversion result. The lower 8 bits of 10-bit resolution are stored. ADCRL can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 12-6. Format of 8-Bit A/D Conversion Result Register L (ADCRL) Address: FF08H Symbol 7 After reset: 00H 6 R 5 4 3 2 1 0 ADCRL Cautions 1.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER (5) Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark A/D converter analog input pins differ depending on products.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER Cautions 1. Be sure to clear bits 4, 5, and 7 to “0”. 2. Set a channel to be used for A/D conversion in the input mode by using port mode registers 1, 2, 7 (PM1, PM2, PM7). 3. Set ADS after PGA operation setting when selecting the PGA output signal as analog input. Set ADS after single AMP operation setting when selecting the operational amplifier output signal as analog input (refer to CHAPTER 13 OPERATIONAL AMPLIFIERS). 4.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER Figure 12-9.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER Figure 12-9.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER Figure 12-10. Format of Port Mode Register 1 (PM1) (78K0/KB2-L, 78K0/KC2-L) Address: FF21H Symbol PM1 After reset: FFH R/W 7 6 5 4 3 2 1 0 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n P1n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Figure 12-11.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER Figure 12-12. Format of Port Mode Register 7 (PM7) (78K0/KA2-L (32-pin products)) Address: FF27H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM7 1 1 1 1 1 PM72 PM71 PM70 PM7n P7n pin I/O mode selection (n = 0 to 2) 0 Output mode (output buffer on) 1 Input mode (output buffer off) R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER When using P10/ANI8/AMP1-, P11/ANI9/AMP1OUT, or P12/ANI10/AMP1+ in the 78K0/KB2-L and 78K0/KC2-L, set the registers according to the pin function to be used (refer to Tables 12-3 and 12-4). Table 12-3. Setting Functions of P10/ANI8/AMP1-, P12/ANI10/AMP1+ Pins ADPC1 Register Analog input PM1 Register Input mode OPAMP1E bit 0 ADS Register P10/ANI8/AMP1-, (n = 8, 10) P12/ANI10/AMP1+ Pins Selects ANIn.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER When using P20/AMP0-/ANI0 to P27/ANI7, set the registers according to the pin function to be used (refer to Tables 12-5 to 12-7). Table 12-5. Setting Functions of P20/ANI0/AMP0-, P22/ANI2/AMP0+ Pins ADPC0 Register Analog input PM2 Register Input mode OPAMP0E bit 0 ADS Register P20/ANI0/AMP0-, (n = 0, 2) P22/ANI2/AMP0+ Pins Selects ANIn. Analog input (to be converted into digital signals) selection Does not select ANIn.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER Table 12-6. Setting Functions of P21/ANI1/AMP0OUT/PGAIN Pin ADPC0 Register PM2 Register OPAMP0E PGAEN bit ADS Register P21/ANI1/AMP0OUT/PGAIN Pin bit Analog I/O Input mode 0 0 Analog input (to be converted into digital Selects ANI1. signals) selection Does not select ANI1. Analog input (not to be converted into digital signals) 0 1 Selects PGAOUT.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER When using P70/ANI8 to P72/ANI10 of 78K0/KA2-L (32-pin products), set the registers according to the pin function to be used (refer to Table 12-8). Table 12-8. Setting Functions of P70/ANI8 to P72/ANI10 Pins ADPC1 Register Analog input PM7 Register Input mode P70/ANI8 to P72/ANI10 Pins Selects ANIn. Setting prohibited Does not select ANIn. Digital input Output mode Selects ANIn. Setting prohibited Does not select ANIn.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER 12.4 A/D Converter Operations 12.4.1 Basic operations of A/D converter <1> Set the A/D conversion time and the operation mode by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of the A/D converter mode register 0 (ADM0). <2> Set bit 0 (ADCE) of ADM0 to 1 to start the operation of the A/D voltage comparator.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER Cautions 1. 2. Remark Make sure the period of <2> to <6> is 1 μs or more. If the timing of <2> is earlier than that of <4>, <2> may be performed any time. Three types of A/D conversion result registers are available. • ADCR (16 bits): Store 10-bit A/D conversion value • ADCRH (8 bits): Store the higher 8-bit A/D conversion value • ADCRL (8 bits): Store the lower 8-bit A/D conversion value Figure 12-13.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER 12.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI10) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression. ADCR = INT ( VAIN AVREF × 1024 + 0.5) or (ADCR − 0.5) × where, INT( ): AVREF 1024 ≤ VAIN < (ADCR + 0.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER Figure 12-14 shows the relationship between the analog input voltage and the A/D conversion result. Figure 12-14. Relationship between Analog Input Voltage and A/D Conversion Result SAR ADCR 1023 03FFH 1022 03FEH 1021 03FDH 3 0003H 2 0002H 1 0001H A/D conversion result 0 0000H 1 1 3 2 5 3 2048 1024 2048 1024 2048 1024 2043 1022 2045 1023 2047 1 2048 1024 2048 1024 2048 Input voltage/AVREF R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER 12.4.3 A/D converter operation mode One channel of analog input is selected from ANI0 to ANI10 and PGA output by the analog input channel specification register (ADS) and A/D conversion is executed. Remark A/D converter analog input pins differ depending on products.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER The setting methods are described below. <1> Set the A/D conversion time and the operation mode by using bits 5 to 1 (FR2 to FR0, LV1, and LV0) of the A/D converter mode register 0 (ADM0). <2> Set bit 0 (ADCE) of ADM0 to 1. <3> Set the channel to be used to analog input by using the A/D port configuration registers 0, 1 (ADPC0, ADPC1) and port mode registers 1, 2 (PM1, PM2).
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER 12.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range). 1LSB is as follows when the resolution is 10 bits.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER 12.6 Cautions for A/D Converter (1) Operating current in STOP mode To satisfy the DC characteristics of the power supply current in STOP mode, clear bits 7 (ADCS) and 0 (ADCE) of A/D converter mode register 0 (ADM0) to 0 before executing a STOP instruction. To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start operation.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER Figure 12-22. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVREF or equal to or lower than AVSS may enter, clamp with a diode with a small VF value (0.3 V or lower).
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the prechange analog input may be set just before the ADS rewrite.
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78K0/Kx2-L CHAPTER 12 A/D CONVERTER (11) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 12-24. Internal Equivalent Circuit of ANIn Pin R1 ANIn C1 C2 Table 12-9. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) AVREF Mode R1 C1 C2 4.0 V ≤ AVREF ≤ 5.5 V Standard 5.2 kΩ 8 pF 6.3 pF High-speed 2 7.8 kΩ High-speed 1 5.2 kΩ Standard 18.6 kΩ High-speed 2 7.8 kΩ Low-voltage 169.8 kΩ 2.7 V ≤ AVREF < 4.0 V 1.
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78K0/Kx2-L CHAPTER 13 OPERATIONAL AMPLIFIERS CHAPTER 13 OPERATIONAL AMPLIFIERS Item Operational amplifier 78K0/KY2-L 78K0/KA2-L 78K0/KB2-L 78K0/KC2-L (μPD78F055x) (μPD78F056x) (μPD78F057x) (μPD78F058x) 16 Pins 20, 25, 32 Pins 30 Pins 40, 44, 48 Pins 1 ch (operational amplifier 0) 2 ch (operational amplifiers 0 and 1) (products with operational amplifier only) 13.
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78K0/Kx2-L CHAPTER 13 OPERATIONAL AMPLIFIERS 13.2 Configuration of Operational Amplifier The operational amplifiers consist of the following hardware. Table 13-1.
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78K0/Kx2-L CHAPTER 13 OPERATIONAL AMPLIFIERS 13.3 Registers Used in Operational Amplifier The operational amplifiers use the following four registers.
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78K0/Kx2-L CHAPTER 13 OPERATIONAL AMPLIFIERS Figure 13-3. Format of Operational Amplifier 1 Control Register (AMP1M) (Products with Operational Amplifier of the 78K0/KB2-L and 78K0/KC2-L Only) Address: FF61H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 0 AMP1M OPAMP1E 0 0 0 0 0 0 0 OPAMP1E Operational amplifier 1 operation control 0 Stops operational amplifier 1 operation 1 Enables operational amplifier 1 (single AMP mode) operation Cautions 1.
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78K0/Kx2-L CHAPTER 13 OPERATIONAL AMPLIFIERS Figure 13-4.
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78K0/Kx2-L CHAPTER 13 OPERATIONAL AMPLIFIERS Cautions 1. Set the pin set to analog I/O to the input mode by using port mode register 2 (PM2). 2. If data is written to ADPC0, a wait cycle is generated. Do not write data to ADPC0 when the peripheral hardware clock is stopped. For details, refer to CHAPTER 31 CAUTIONS FOR WAIT. Figure 13-5.
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78K0/Kx2-L Caution CHAPTER 13 OPERATIONAL AMPLIFIERS 3. Set ADS after PGA operation setting when selecting the PGA output signal as analog input. Set ADS after single AMP operation setting when selecting the operational amplifier output signal as analog input. (4) Port mode registers 1, 2 (PM1, PM2) When using AMP0-/ANI0/P20, AMP0OUT/PGAIN/ANI1/P21, and AMP0+/ANI2/P22 pins for the operational amplifier 0, set PM20 to PM22 to 1.
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78K0/Kx2-L CHAPTER 13 OPERATIONAL AMPLIFIERS Figure 13-8. Format of Port Mode Register 2 (PM2) (a) 78K0/KY2-L Address: FF22H After reset: FFH R/W Symbol 7 6 5 4 3 2 1 0 PM2 1 1 1 1 PM23 PM22 PM21 PM20 5 4 3 2 1 0 PM25 PM24 PM23 PM22 PM21 PM20 Caution Be sure to set bits 4 to 7 of PM2 to 1. (b) 78K0/KA2-L Address: FF22H Symbol PM2 After reset: FFH 7 R/W 6 PM27 Note 1 PM26 Note 2 Notes 1. 32-pin products only 2.
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78K0/Kx2-L CHAPTER 13 OPERATIONAL AMPLIFIERS When using P10/ANI8/AMP1-, P11/ANI9/AMP1OUT, or P12/ANI10/AMP1+ in the 78K0/KB2-L and 78K0/KC2-L, set the registers according to the pin function to be used (refer to Tables 13-2 and 13-3). Table 13-2. Setting Functions of P10/ANI8/AMP1-, P12/ANI10/AMP1+ Pins ADPC1 Register Analog input PM1 Register Input mode OPAMP1E bit 0 ADS Register P10/ANI8/AMP1-, (n = 8, 10) P12/ANI10/AMP1+ Pins Selects ANIn.
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78K0/Kx2-L CHAPTER 13 OPERATIONAL AMPLIFIERS When using P20/ANI0/AMP0-, P21/ANI1/AMP0OUT/PGAIN, and P22/ANI2/AMP0+, set the registers according to the pin function to be used (refer to Tables 13-4 and 13-5). Table 13-4. Setting Functions of P20/ANI0/AMP0-, P22/ANI2/AMP0+ Pins ADPC0 Register Analog input PM2 Register Input mode OPAMP0E bit 0 ADS Register P20/ANI0/AMP0-, (n = 0, 2) P22/ANI2/AMP0+ Pins Selects ANIn.
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78K0/Kx2-L CHAPTER 13 OPERATIONAL AMPLIFIERS Table 13-5. Setting Functions of P21/ANI1/AMP0OUT/PGAIN Pin ADPC0 Register PM2 Register OPAMP0E PGAEN bit ADS Register P21/ANI1/AMP0OUT/PGAIN Pin bit Analog I/O Input mode 0 0 Selects ANI1. Analog input (to be converted into digital signals) selection Does not select ANI1. Analog input (not to be converted into digital signals) 0 1 Selects PGAOUT. PGA input (PGA output is converted into digital signals) Selects ANI1.
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78K0/Kx2-L CHAPTER 13 OPERATIONAL AMPLIFIERS 13.4 Operational Amplifier Operations The operational amplifiers 0 and 1 have the following mode. • Single AMP mode (operational amplifiers 0 and 1) • PGA (Programmable gain amplifier) mode (operational amplifier 0 only) 13.4.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 CHAPTER 14 SERIAL INTERFACE UART6 14.1 Functions of Serial Interface UART6 Serial interface UART6 are mounted onto all 78K0/Kx2-L microcontroller products. Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, refer to 14.4.1 Operation stop mode.
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78K0/Kx2-L Remark CHAPTER 14 SERIAL INTERFACE UART6 LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master. The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the LIN master via the LIN network.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-2. LIN Reception Operation Wakeup signal frame Sync break field Sync field Identifier field Data field Data field Checksum field 13-bit SBF reception SF reception ID reception Data reception Data reception LIN Bus <5> <2> RXD6 (input) Disable Data reception Enable <3> Reception interrupt (INTSR6) <1> Edge detection (INTP0) <4> Capture timer Disable Enable Reception processing is as follows.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-3.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-3.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 The peripheral functions used in the LIN communication operation are shown below. • External interrupt (INTP0); wakeup signal detection Use: Detects the wakeup signal edges and detects start of communication.
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78K0/Kx2-L TI000, INTP0Note Filter INTSR6 fPRS fPRS/2 fPRS/22 fPRS/23 fPRS/24 fPRS/25 fPRS/26 fPRS/27 fPRS/28 fPRS/29 fPRS/210 8-bit timer/ event counter 50 output Asynchronous serial interface operation mode register 6 (ASIM6) Asynchronous serial interface reception error status register 6 (ASIS6) fXCLK6 Baud rate generator RXD6/ P14 Reception control INTSRE6 Selector (1) Receive buffer register 6 (RXB6) R01UH0028EJ0400 Rev.4.00 Sep 27, 2010 Figure 14-4.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from RXS6. If the data length is set to 7 bits, data is transferred as follows. • In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 14.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following ten registers.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (1/2) Address: FF50H After reset: 01H R/W Symbol <7> <6> <5> 4 3 2 1 0 ASIM6 POWER6 TXE6 RXE6 PS61 PS60 CL6 SL6 ISRM6 POWER6 0 Note 1 Enables/disables operation of internal operation clock Disables operation of the internal operation clock (fixes the clock to low level) and asynchronously resets the internal circuit 1 Note 2 .
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) PS61 PS60 Transmission operation 0 0 Does not output parity bit. Reception without parity 0 1 Outputs 0 parity. Reception as 0 parity 1 0 Outputs odd parity. Judges as odd parity. 1 1 Outputs even parity. Judges as even parity.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation, or clearing bit 7 (POWER6) or bit 5 (RXE6) of ASIM6 to 0 clears this register to 00H. 00H is read when this register is read.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-8. Format of Clock Selection Register 6 (CKSR6) Address: FF56H After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 CKSR6 0 0 0 0 TPS63 TPS62 TPS61 TPS60 TPS63 TPS62 TPS61 TPS60 Base clock (fXCLK6) selection fPRS = 2 MHz fPRS = 10 MHz 0 0 0 0 fPRS 2 MHz 5 MHz 10 MHz 0 0 0 1 fPRS/2 1 MHz 2.5 MHz 5 MHz 0 0 1 0 fPRS/2 2 500 kHz 1.25 MHz 2.5 MHz fPRS/2 3 250 kHz 625 kHz 1.25 MHz fPRS/2 4 125 kHz 312.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1). Figure 14-9.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 16H.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) SBL62 SBL61 SBL60 SBF transmission output width control 1 0 1 SBF is output with 13-bit length. 1 1 0 SBF is output with 14-bit length. 1 1 1 SBF is output with 15-bit length. 0 0 0 SBF is output with 16-bit length. 0 0 1 SBF is output with 17-bit length. 0 1 0 SBF is output with 18-bit length. 0 1 1 SBF is output with 19-bit length.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 (7) Input switch control register (ISC) The input switch control register (ISC) is used to receive a status signal transmitted from the master during LIN (Local Interconnect Network) reception. The signal input from the RXD6 pin is selected as the input source of INTP0 and TI000 when ISC0 and ISC1 are set to 1 (refer to Figure 14-3 Port Configuration for LIN Reception Operation). This register can be set by a 1-bit or 8-bit memory manipulation instruction.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-12. Format of Port Mode Register 1 (PM1) Address: FF21H Symbol PM1 After reset: FFH R/W 7 6 5 4 3 2 1 0 PM17 PM16 PM15 PM14 PM13 PM12 PM11 PM10 PM1n P1n pin I/O mode selection (n = 0 to 7) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Remark The figure shown above presents the format of port mode register 1 (PM1) of the 78K0/KB2-L and 78K0/KC2-L. Figure 14-13.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 14.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 14.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER6, TXE6, and RXE6) of ASIM6 to 0.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 14.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 The relationship between the register settings and pins is shown below. Table 14-2.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 14-15 and 14-16 show the format and waveform example of the normal transmit/receive data. Figure 14-15. Format of Normal UART Transmit/Receive Data 1. LSB-first transmission/reception 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit D1 D0 Parity bit Stop bit Character bits 2.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-16. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. Caution Fix the PS61 and PS60 bits to 0 when the device is used in LIN communication operation.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 (c) Normal transmission When bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6).
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-18 shows an example of the continuous transmission processing flow. Figure 14-18. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? Yes No Read ASIF6 TXBF6 = 0? No Yes Write TXB6.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-19 shows the timing of starting continuous transmission, and Figure 14-20 shows the timing of ending continuous transmission. Figure 14-19. Timing of Starting Continuous Transmission Start TXD6 Data (1) Parity Stop Start Data (2) Parity Stop Start INTST6 TXB6 FF TXS6 FF Data (1) Data (2) Data (1) Data (3) Data (2) Data (3) TXBF6 Note TXSF6 Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-20.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6 pin input is detected.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RxD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 14-23, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 14-23.
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78K0/Kx2-L (i) CHAPTER 14 SERIAL INTERFACE UART6 SBF reception When the device is used in LIN communication operation, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, refer to Figure 14-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 14.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-26.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 14.4.4 Calculation of baud rate (1) Baud rate calculation expression The baud rate can be calculated by the following expression. • Baud rate = fXCLK6 2×k [bps] fXCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 4, 5, 6, ..., 255) Table 14-4.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 (2) Error of baud rate The baud rate error can be calculated by the following expression. • Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) − 1 × 100 [%] Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 14-27.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 Minimum permissible data frame length: FLmin = 11 × FL − k−2 2k × FL = 21k + 2 2k FL Therefore, the maximum receivable baud rate at the transmission destination is as follows. 22k BRmax = (FLmin/11)−1 = Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows.
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78K0/Kx2-L CHAPTER 14 SERIAL INTERFACE UART6 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected. Figure 14-28.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA CHAPTER 15 SERIAL INTERFACE IICA 15.1 Functions of Serial Interface IICA Serial interface IICA is mounted onto all 78K0/Kx2-L microcontroller products. Serial interface IICA has the following three modes. (1) Operation stop mode This mode is used when serial transfers are not performed. It can therefore be used to reduce power consumption.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-1.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-2 shows a serial bus configuration example. Figure 15-2. Serial Bus Configuration Example Using I2C Bus + VDD + VDD Master CPU1 SDAA0 Slave CPU1 Address 0 SCLA0 Serial data bus Serial clock SDAA0 Slave CPU2 SCLA0 SDAA0 SCLA0 SDAA0 SCLA0 SDAA0 SCLA0 R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA 15.2 Configuration of Serial Interface IICA Serial interface IICA includes the following hardware. Table 15-1.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-4. Format of Slave Address Register 0 (SVA0) Address: FFA6H Symbol 7 After reset: 00H 6 R/W 5 4 3 2 1 0 0Note SVA0 Note Bit 0 is fixed to 0. (3) SO latch The SO latch is used to retain the SDAA0 pin’s output level. (4) Wakeup controller This circuit generates an interrupt request (INTIICA0) when the address received by this register matches the address value set to the slave address register 0 (SVA0) or when an extension code is received.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (13) Bus status detector This circuit detects whether or not the bus is released by detecting start conditions and stop conditions. However, as the bus status cannot be detected immediately following operation, the initial status is set by the STCEN bit.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-5. Format of IICA Control Register 0 (IICACTL0) (1/4) Address: FFA7H After reset: 00H R/W Symbol <7> <6> <5> <4> <3> <2> <1> <0> IICACTL0 IICE0 LREL0 WREL0 SPIE0 WTIM0 ACKE0 STT0 SPT0 2 IICE0 I C operation enable 0 Stop operation. Reset the IICA status register 0 (IICAS0) 1 Enable operation. Note 1 . Stop internal operation. Be sure to set this bit (1) while the SCLA0 and SDLA0 lines are at high level.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-5. Format of IICA Control Register 0 (IICACTL0) (2/4) Note 1 SPIE0 Enable/disable generation of interrupt request when stop condition is detected 0 Disable 1 Enable If the WUP bit of the IICA control register 1 (IICACTL1) is 1, no stop condition interrupt will be generated even if SPIE0 = 1.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-5. Format of IICA Control Register 0 (IICACTL0) (3/4) STT0 Note Start condition trigger 0 Do not generate a start condition. 1 When bus is released (in standby state, when IICBSY = 0): If this bit is set (1), a start condition is generated (startup as the master). When a third party is communicating: • When communication reservation function is enabled (IICRSV = 0) Functions as the start condition reservation flag.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-5. Format of IICA Control Register 0 (IICACTL0) (4/4) SPT0 Stop condition trigger 0 Stop condition is not generated. 1 Stop condition is generated (termination of master device’s transfer). Cautions concerning set timing • For master reception: Cannot be set to 1 during transfer. Can be set to 1 only in the waiting period when ACKE0 has been cleared to 0 and slave has been notified of final reception.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (2) IICA status register 0 (IICAS0) This register indicates the status of I2C. This register is read by a 1-bit or 8-bit memory manipulation instruction only when STT0 = 1 and during the wait period. Reset signal generation clears this register to 00H. Caution Reading the IICAS0 register while the address match wakeup function is enabled (WUP = 1) in STOP mode is prohibited.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-6. Format of IICA Status Register 0 (IICAS0) (2/3) EXC0 Detection of extension code reception 0 Extension code was not received. 1 Extension code was received.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-6. Format of IICA Status Register 0 (IICAS0) (3/3) ACKD0 Detection of acknowledge (ACK) 0 Acknowledge was not detected. 1 Acknowledge was detected.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-7.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (4) IICA control register 1 (IICACTL1) This register is used to set the operation mode of I2C and detect the statuses of the SCLA0 and SDAA0 pins. This register can be set by a 1-bit or 8-bit memory manipulation instruction. However, the CLD0 and DAD0 bits are read-only. 2 Set the IICACTL1 register, except the WUP bit, while operation of I C is disabled (bit 7 (IICE0) of IICA control register 0 (IICACTL0) is 0).
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-8. Format of IICA Control Register 1 (IICACTL1) (2/2) CLD0 Detection of SCLA0 pin level (valid only when IICE0 = 1) 0 The SCLA0 pin was detected at low level. 1 The SCLA0 pin was detected at high level.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (5) IICA low-level width setting register (IICWL) This register is used to set the low-level width of the SCLA0 pin signal that is output by serial interface IICA being in master mode. This register can be set by an 8-bit memory manipulation instruction. 2 Set this register while operation of I C is disabled (bit 7 (IICE0) of the IICA control register 0 (IICACTL0) is 0). Reset signal generation sets this register to FFH. Figure 15-9.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (8) Port output mode register 6 (POM6) 2 This register sets the output mode of P60 to P63 in 1-bit units. During I C communication, set POM60 and POM61 to 1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 15-12.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA 15.4 I2C Bus Mode Functions 15.4.1 Pin configuration The serial clock pin (SCLA0) and serial data bus pin (SDAA0) are configured as follows. (1) SCLA0 .... This pin is used for serial clock input and output. This pin is an N-ch open-drain output for both master and slave devices. Input is Schmitt input. (2) SDAA0 .... This pin is used for serial data input and output. This pin is an N-ch open-drain output for both master and slave devices.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA 15.4.2 Setting transfer clock by using IICWL and IICWH registers (1) Setting transfer clock on master side Transfer clock = fPRS IICWL + IICWH + fPRS (tR + tF) At this time, the optimal setting values of the IICWL and IICWH registers are as follows. (The fractional parts of all setting values are rounded up.) • When the fast mode 0.52 × fPRS Transfer clock 0.48 − tR − tF) × fPRS IICWH = ( Transfer clock IICWL = • When the normal mode 0.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA 15.5 I2C Bus Definitions and Control Methods The following section describes the I2C bus’s serial data communication format and the signals used by the I2C bus. Figure 15-15 shows the transfer timing for the “start condition”, “address”, “data”, and “stop condition” output via the I2C bus’s serial data bus. Figure 15-15.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA 15.5.2 Addresses The address is defined by the 7 bits of data that follow the start condition. An address is a 7-bit data segment that is output in order to select one of the slave devices that are connected to the master device via the bus lines. Therefore, each slave device connected via the bus lines must have a unique address.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA 15.5.4 Acknowledge (ACK) ACK is used to check the status of serial data at the transmission and reception sides. The reception side returns ACK each time it has received 8-bit data. The transmission side usually receives ACK after transmitting 8-bit data. When ACK is returned from the reception side, it is assumed that reception has been correctly performed and processing is continued.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA 15.5.5 Stop condition When the SCLA0 pin is at high level, changing the SDAA0 pin from low level to high level generates a stop condition. A stop condition is a signal that the master device generates to the slave device when serial transfer has been completed. When the device is used as a slave, stop conditions can be detected. Figure 15-20.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA 15.5.6 Wait The wait is used to notify the communication partner that a device (master or slave) is preparing to transmit or receive data (i.e., is in a wait state). Setting the SCLA0 pin to low level notifies the communication partner of the wait state. When wait state has been canceled for both the master and slave devices, the next data transfer can begin. Figure 15-21.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-21.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA 15.5.7 Canceling wait The I2C usually cancels a wait state by the following processing.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA 15.5.8 Interrupt request (INTIICA0) generation timing and wait control The setting of bit 3 (WTIM0) of IICA control register 0 (IICACTL0) determines the timing by which INTIICA0 is generated and the corresponding wait control, as shown in Table 15-2. Table 15-2.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (5) Stop condition detection INTIICA0 is generated when a stop condition is detected (only when SPIE0 = 1). 15.5.9 Address match detection method In I2C bus mode, the master device can select a particular slave device by transmitting the corresponding slave address. Address match can be detected automatically by hardware.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA 15.5.12 Arbitration When several master devices simultaneously generate a start condition (when the STT0 bit is set to 1 before the STD0 bit is set to 1), communication among the master devices is performed as the number of clocks are adjusted until the data differs. This kind of operation is called arbitration.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Table 15-4.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA 15.5.13 Wakeup function The I2C bus slave function is a function that generates an interrupt request signal (INTIICA0) when a local address and extension code have been received. This function makes processing more efficient by preventing unnecessary INTIICA0 signal from occurring when addresses do not match. When a start condition is detected, wakeup standby mode is set.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-24. Flow When Setting WUP = 0 upon Address Match (Including Extension Code Reception) STOP mode state Note No INTIICA0 = 1? Yes WUP = 0 Wait Waits for 5 clocks. Reading IICAS0 Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA. Note Perform the processing after “INTIICA0 = 1?” also when an INTIICA0 vector interrupt occurs.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-25. When Releasing STOP Mode other than by INTIICA0 START SPIE0 = 1 WUP = 1 Wait Waits for 3 clocks. STOP instruction STOP mode state Releasing STOP mode Releases STOP mode by an interrupt other than INTIICA0. Note Yes INTIICA0 = 1? No Interrupt servicing WUP = 0 Wait Waits for 5 clocks. Reading IICAS0 Executes processing corresponding to the operation to be executed after checking the operation state of serial interface IICA.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA 15.5.14 Communication reservation (1) When communication reservation function is enabled (bit 0 (IICRSV) of IICA flag register 0 (IICAF0) = 0) To start master device communications when not currently using a bus, a communication reservation can be made to enable transmission of a start condition when the bus is released. There are two modes under which the bus is not used.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-26 shows the communication reservation timing. Figure 15-26.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-28. Communication Reservation Protocol DI SET1 STT0 Define communication reservation Wait (Communication reservation)Note 2 MSTS0 = 0? Yes Sets STT0 flag (communication reservation) Defines that communication reservation is in effect (defines and sets user flag to any part of RAM) Secures wait timeNote 1 by software.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (2) When communication reservation function is disabled (bit 0 (IICRSV) of IICA flag register 0 (IICAF0) = 1) When bit 1 (STT0) of the IICA control register 0 (IICACTL0) is set to 1 when the bus is not used in a communication during bus communication, this request is rejected and a start condition is not generated. The following two statuses are included in the status where bus is not used.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA 15.5.15 Cautions (1) When STCEN (bit 1 of IICA flag register 0 (IICAF0)) = 0 Immediately after I2C operation is enabled (IICE0 = 1), the bus communication status (the IICBSY flag (bit 6 of the IICAF0 register) = 1) is recognized regardless of the actual bus status.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA 15.5.16 Communication operations The following shows three operation procedures with the flowchart. (1) Master operation in single master system The flowchart when using the 78K0/Kx2-L microcontrollers as the master in a single master system is shown below. This flowchart is broadly divided into the initial settings and communication processing. Execute the initial settings at startup.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (1) Master operation in single-master system Figure 15-29. Master Operation in Single-Master System START Initializing I2C busNote Setting of the port used alternatively as the pin to be used. First, set the port to input mode and the output latch to 0 (see 15.3 (9) Port mode register 6 (PM6)). Initial setting Setting port IICWL, IICWH ← XXH Sets a transfer clock. SVA0 ← XXH Sets a local address.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (2) Master operation in multi-master system Figure 15-30. Master Operation in Multi-Master System (1/3) START Setting of the port used alternatively as the pin to be used. First, set the port to input mode and the output latch to 0 (see 15.3 (9) Port mode register 6 (PM6)). Setting port IICWL, IICWH ← XXH Selects a transfer clock. SVA0 ← XXH Sets a local address. IICAF0 ← 0XH Setting STCEN and IICRSV Sets a start condition.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-30. Master Operation in Multi-Master System (2/3) A Enables reserving communication. STT0 = 1 Secure wait timeNote by software. Wait Communication processing Prepares for starting communication (generates a start condition). MSTS0 = 1? No Yes INTIICA0 interrupt occurs? No Waits for bus release (communication being reserved).
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-30. Master Operation in Multi-Master System (3/3) C Writing IICA INTIICA0 interrupt occurs? Starts communication (specifies an address and transfer direction). No Waits for detection of ACK. Yes MSTS0 = 1? No Yes No 2 ACKD0 = 1? Yes TRC0 = 1? No ACKE0 = 1 WTIM0 = 0 Yes Communication processing WTIM0 = 1 WREL0 = 1 Writing IICA INTIICA0 interrupt occurs? INTIICA0 interrupt occurs? No Waits for data transmission.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Basically, the slave operation is event-driven. Therefore, processing by the INTIICA0 interrupt (processing that must substantially change the operation status such as detection of a stop condition during communication) is necessary. In the following explanation, it is assumed that the extension code is not supported for data communication.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA The main processing of the slave operation is explained next. Start serial interface IICA and wait until communication is enabled. When communication is enabled, execute communication by using the communication mode flag and ready flag (processing of the stop condition and start condition is performed by an interrupt. Here, check the status by using the flags). The transmission operation is repeated until the master no longer returns ACK.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA An example of the processing procedure of the slave with the INTIICA0 interrupt is explained below (processing is performed assuming that no extension code is used). The INTIICA0 interrupt checks the status, and the following operations are performed. <1> Communication is stopped if the stop condition is issued. <2> If the start condition is issued, the address is checked and communication is completed if the address does not match.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA 2 15.5.17 Timing of I C interrupt request (INTIICA0) occurrence The timing of transmitting or receiving data and generation of interrupt request signal INTIICA0, and the value of the IICAS0 register when the INTIICA0 signal is generated are shown below. Remark ST: Start condition AD6 to AD0: Address R/W: Transfer direction specification ACK: Acknowledge D7 to D0: Data SP: Stop condition R01UH0028EJ0400 Rev.4.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (1) Master device operation (a) Start ~ Address ~ Data ~ Data ~ Stop (transmission/reception) (i) When WTIM0 = 0 SPT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 5 1: IICAS0 = 1000×110B 2: IICAS0 = 1000×000B 3: IICAS0 = 1000×000B (Sets WTIM0 to 1)Note 4: IICAS0 = 1000××00B (Sets SPT0 to 1)Note 5: IICAS0 = 00000001B Note To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIICA0 interrupt reques
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (restart) (i) When WTIM0 = 0 STT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST 2 3 SPT0 = 1 ↓ AD6 to AD0 R/W ACK D7 to D0 4 ACK SP 5 6 7 1: IICAS0 = 1000×110B 2: IICAS0 = 1000×000B (Sets WTIM0 to 1)Note 1 3: IICAS0 = 1000××00B (Clears WTIM0 to 0Note 2, sets STT0 to 1) 4: IICAS0 = 1000×110B 5: IICAS0 = 1000×000B (Sets WTIM0 to 1)Note 3 6: IICAS0 = 1000××00B (Sets SPT0 to 1) 7: IICAS0 = 000
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Data ~ Stop (extension code transmission) (i) When WTIM0 = 0 SPT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 5 1: IICAS0 = 1010×110B 2: IICAS0 = 1010×000B 3: IICAS0 = 1010×000B (Sets WTIM0 to 1)Note 4: IICAS0 = 1010××00B (Sets SPT0 to 1) 5: IICAS0 = 00000001B Note To generate a stop condition, set WTIM0 to 1 and change the timing for generating the INTIICA0 interrupt request signal.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (2) Slave device operation (slave address data reception) (a) Start ~ Address ~ Data ~ Data ~ Stop (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICAS0 = 0001×110B 2: IICAS0 = 0001×000B 3: IICAS0 = 0001×000B 4: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK D7 to D0 2 ACK SP 3 4 1: IICAS0 = 0001×110B 2: II
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (b) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches with SVA0) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICAS0 = 0001×110B 2: IICAS0 = 0001×000B 3: IICAS0 = 0001×110B 4: IICAS0 = 0001×000B 5: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, matches with SVA0) ST AD6 to AD0 R
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (c) Start ~ Address ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST 2 AD6 to AD0 R/W ACK D7 to D0 3 ACK SP 4 5 1: IICAS0 = 0001×110B 2: IICAS0 = 0001×000B 3: IICAS0 = 0010×010B 4: IICAS0 = 0010×000B 5: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, does not match
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (d) Start ~ Address ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3 4 1: IICAS0 = 0001×110B 2: IICAS0 = 0001×000B 3: IICAS0 = 00000110B 4: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, does not match address (= not ex
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (3) Slave device operation (when receiving extension code) The device is always participating in communication when it receives an extension code.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (b) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, matches SVA0) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICAS0 = 0010×010B 2: IICAS0 = 0010×000B 3: IICAS0 = 0001×110B 4: IICAS0 = 0001×000B 5: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, matches SVA0) ST AD6 to AD0 R/W ACK 1 D7
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (c) Start ~ Code ~ Data ~ Start ~ Code ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, extension code reception) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 3 ACK SP 4 5 1: IICAS0 = 0010×010B 2: IICAS0 = 0010×000B 3: IICAS0 = 0010×010B 4: IICAS0 = 0010×000B 5: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, extension code reception) ST AD
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (d) Start ~ Code ~ Data ~ Start ~ Address ~ Data ~ Stop (i) When WTIM0 = 0 (after restart, does not match address (= not extension code)) ST AD6 to AD0 R/W ACK D7 to D0 1 ACK ST AD6 to AD0 R/W ACK 2 D7 to D0 ACK SP 3 4 1: IICAS0 = 00100010B 2: IICAS0 = 00100000B 3: IICAS0 = 00000110B 4: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 (after restart, does not match address (= not exte
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (4) Operation without communication (a) Start ~ Code ~ Data ~ Data ~ Stop ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 1: IICAS0 = 00000001B Remark : Generated only when SPIE0 = 1 (5) Arbitration loss operation (operation as slave after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt request signal INTIICA0 has occurred to check the arbitration result.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 ACK 2 SP 3 4 1: IICAS0 = 0101×110B 2: IICAS0 = 0001×100B 3: IICAS0 = 0001××00B 4: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (b) When arbitration loss occurs during transmission of extension code (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 SP 4 1: IICAS0 = 0110×010B 2: IICAS0 = 0010×000B 3: IICAS0 =
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK 1 D7 to D0 ACK 2 D7 to D0 ACK 3 SP 4 5 1: IICAS0 = 0110×010B 2: IICAS0 = 0010×110B 3: IICAS0 = 0010×100B 4: IICAS0 = 0010××00B 5: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (6) Operation when arbitration loss occurs (no communication after arbitration loss) When the device is used as a master in a multi-master system, read the MSTS0 bit each time interrupt req
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (b) When arbitration loss occurs during transmission of extension code ST AD6 to AD0 R/W ACK D7 to D0 ACK D7 to D0 ACK SP 1 2 1: IICAS0 = 0110×010B Sets LREL0 = 1 by software 2: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (c) When arbitration loss occurs during transmission of data (i) When WTIM0 = 0 ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK SP 3 1: IICAS0 = 10001110B 2: IICAS0 = 01000
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (ii) When WTIM0 = 1 ST AD6 to AD0 R/W ACK D7 to D0 ACK 1 D7 to D0 ACK SP 2 3 1: IICAS0 = 10001110B 2: IICAS0 = 01000100B 3: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 (d) When loss occurs due to restart condition during data transfer (i) Not extension code (Example: unmatches with SVA0) ST AD6 to AD0 R/W ACK D7 to Dn ST 1 AD6 to AD0 R/W ACK D7 to D0 2 ACK SP 3 1: IICAS0 = 1000×110B 2: IICAS0 = 01000110B 3:
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (ii) Extension code ST AD6 to AD0 R/W ACK D7 to Dn ST AD6 to AD0 R/W ACK 1 2 D7 to D0 ACK SP 3 1: IICAS0 = 1000×110B 2: IICAS0 = 01100010B Sets LREL0 = 1 by software 3: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care n = 6 to 0 (e) When loss occurs due to stop condition during data transfer ST AD6 to AD0 R/W ACK D7 to Dn SP 1 2 1: IICAS0 = 10000110B 2: IICAS0 = 01000001B Remark : Always generated
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (f) When arbitration loss occurs due to low-level data when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 3 ACK D7 to D0 ACK SP 4 5 1: IICAS0 = 1000×110B 2: IICAS0 = 1000×000B (Sets WTIM0 to 1) 3: IICAS0 = 1000×100B (Clears WTIM0 to 0) 4: IICAS0 = 01000000B 5: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 STT
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (g) When arbitration loss occurs due to a stop condition when attempting to generate a restart condition (i) When WTIM0 = 0 STT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 SP 3 4 1: IICAS0 = 1000×110B 2: IICAS0 = 1000×000B (Sets WTIM0 to 1) 3: IICAS0 = 1000××00B (Sets STT0 to 1) 4: IICAS0 = 01000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 STT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK SP 2 3
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA (h) When arbitration loss occurs due to low-level data when attempting to generate a stop condition (i) When WTIM0 = 0 SPT0 = 1 ↓ ST AD6 to AD0 R/W ACK D7 to D0 1 ACK 2 D7 to D0 ACK 3 D7 to D0 ACK SP 4 5 1: IICAS0 = 1000×110B 2: IICAS0 = 1000×000B (Sets WTIM0 to 1) 3: IICAS0 = 1000×100B (Clears WTIM0 to 0) 4: IICAS0 = 01000100B 5: IICAS0 = 00000001B Remark : Always generated : Generated only when SPIE0 = 1 ×: Don’t care (ii) When WTIM0 = 1 SPT0
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA 15.6 Timing Charts When using the I2C bus mode, the master device outputs an address via the serial bus to select one of several slave devices as its communication partner. After outputting the slave address, the master device transmits the TRC0 bit (bit 3 of the IICA status register 0 (IICAS0)), which specifies the data transfer direction, and then starts serial communication with the slave device.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-33.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-33.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-33.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-34.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-34.
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78K0/Kx2-L CHAPTER 15 SERIAL INTERFACE IICA Figure 15-34.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Item 78K0/KY2-L 78K0/KA2-L 78K0/KB2-L 78K0/KC2-L (μPD78F055x) (μPD78F056x) (μPD78F057x) (μPD78F058x) 16 pins 20 pins 25, 32 pins 30 pins 40, 44, 48 pins Serial interface CSI10 − − − √ √ Serial interface CSI11 − − √ − √ Remark √: Mounted, −: Not mounted 16.1 Functions of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 have the following two modes.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.2 Configuration of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 include the following hardware. Table 16-1.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-2. Block Diagram of Serial Interface CSI11 (78K0/KC2-L) Internal bus SI11/SDAA0/P61Note 1 8 8 Serial I/O shift register 11 (SIO11) Transmit buffer register 11 (SOTB11) Transmit data controller Output selector SO11 output SO11/P62Note 1 Output latch (P62) Output latch SSI11Note 2 PM60 PM62 Output latch (P60) Transmit controller SCK11/SCLA0/P60Note 1 SSI11Note 2 Notes 1. 2.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (1) Transmit buffer register 1n (SOTB1n) This register sets the transmit data. Transmission/reception is started by writing data to SOTB1n when bit 7 (CSIE1n) and bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1. The data written to SOTB1n is converted from parallel data into serial data by serial I/O shift register 1n, and output to the serial output pin (SO1n).
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (2) Serial I/O shift register 1n (SIO1n) This is an 8-bit register that converts data from parallel data into serial data and vice versa. This register can be read by an 8-bit memory manipulation instruction. Reception is started by reading data from SIO1n if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 0. During reception, the data is read from the serial input pin (SI1n) to SIO1n.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-4. Format of Serial Operation Mode Register 10 (CSIM10) (78K0/KB2-L and 78K0/KC2-L) Address: FF80H After reset: 00H R/W Note 1 Symbol <7> 6 5 4 3 2 1 0 CSIM10 CSIE10 TRMD10 0 DIR10 0 0 0 CSOT10 CSIE10 Operation control in 3-wire serial I/O mode Note 2 0 Disables operation 1 Enables operation and asynchronously resets the internal circuit Note 4 TRMD10 0 Note 5 1 DIR10 6. .
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-5. Format of Serial Operation Mode Register 11 (CSIM11) (78K0/KA2-L (25, 32-pin products), 78K0/KC2-L) Address: FF88H After reset: 00H R/W Symbol <7> CSIM11 Note 1 6 CSIE11 TRMD11 5 SSE11 Note 2 CSIE11 0 Disables operation 1 Enables operation Note 5 1 SSE11 0 DIR11 0 0 0 CSOT11 Note 4 . Transmit/receive mode control Receive mode (transmission disabled).
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (2) Serial clock selection register 1n (CSIC1n) This register specifies the timing of the data transmission/reception and sets the serial clock. CSIC1n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Remark 78K0/KA2-L (25, 32-pin products): n = 1 78K0/KB2-L: n=0 78K0/KC2-L: n = 0, 1 Figure 16-6.
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78K0/Kx2-L Note 2. CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Do not start communication with the external clock from the SCK10 pin when the internal high-speed oscillation clock and high-speed system clock are stopped while the CPU operates with the subsystem clock, or when in the STOP mode. Cautions 1. Do not write to CSIC10 while CSIE10 = 1 (operation enabled). 2. To use P10/SCK10 and P12/SO10 as general-purpose ports, set CSIC10 in the default status (00H). 3.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-7.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Cautions 1. Do not write to CSIC11 while CSIE11 = 1 (operation enabled). 2. To use P62/SO11 and P60/SCK11/SCLA0 as general-purpose ports when CSISEL = 0, set CSIC11 in the default status (00H). To use P120/SO11/INTP0/EXLVI and P40/SCK11/RTCCL/RTCDIV as general-purpose ports when CSISEL = 1, set CSIC11 in the default status (00H). To use P37/SO11, P35/SCK11, and P02/SSI11/INTP5 as general-purpose ports, set CSIM11 in the default status (00H). 3.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (4) Port mode registers 0, 1, 3, 4, 6, 12 (PM0, PM1, PM3, PM4, PM6, PM12) These registers set input/output of ports 0, 1, 3, 4, 6, and 12 in 1-bit units. • 78K0/KA2-L (25, 32-pin products) When using P35/SCK11 as the clock output pin of the serial interface, clear PM35 to 0, and set the output latches of P35 to 1. When using P37/SO11 as the data output pin of the serial interface, clear PM37 and the output latches of P37 to 0.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 PM0, PM1, PM3, PM4, PM6, and PM12 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 16-9. Format of Port Mode Register 0 (PM0) Address: FF20H Symbol PM0 After reset: FFH 7 6 1 R/W 5 1 4 1 PM0n 1 3 1 2 PM02 1 PM01 0 Note 1 PM00 Note 2 P1n pin I/O mode selection (n = 0 to 2) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Notes 1.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-12. Format of Port Mode Register 4 (PM4) Address: FF24H Symbol PM4 After reset: FFH 7 6 1 R/W 5 1 4 1 PM4n 1 3 1 2 PM42 1 Note 1 PM41 0 Note 2 PM40 Note 2 P4n pin I/O mode selection (n = 0 to 2) 0 Output mode (output buffer on) 1 Input mode (output buffer off) Notes 1. 48-pin products only 2. 44-pin and 48-pin products only Remark The figure shown above presents the format of port mode register 4 of the 78K0/KC2-L.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 16.4 Operation of Serial Interfaces CSI10 and CSI11 Serial interfaces CSI10 and CSI11 can be used in the following two modes. • Operation stop mode • 3-wire serial I/O mode 16.4.1 Operation stop mode Serial communication is not executed in this mode. Therefore, the power consumption can be reduced. In addition, the SCK1n, SI1n, SO1n, and SSI11 pins can be used as ordinary I/O port pins in this mode.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 • Serial operation mode register 11 (CSIM11) Address: FF88H After reset: 00H R/W Symbol <7> 6 5 4 3 2 1 0 CSIM11 CSIE11 TRMD11 SSE11 DIR11 0 0 0 CSOT11 CSIE11 0 Notes 1. Operation control in 3-wire serial I/O mode Note 1 Disables operation and asynchronously resets the internal circuit Note 2 .
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 The relationship between the register settings and pins is shown below. Table 16-2.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Table 16-2.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Table 16-2.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Table 16-2.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (2) Communication operation In the 3-wire serial I/O mode, data is transmitted or received in 8-bit units. Each bit of the data is transmitted or received in synchronization with the serial clock. Data can be transmitted or received if bit 6 (TRMD1n) of serial operation mode register 1n (CSIM1n) is 1. Transmission/reception is started when a value is written to transmit buffer register 1n (SOTB1n).
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-15. Timing in 3-Wire Serial I/O Mode (1/2) (a) Transmission/reception timing (Type 1: TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 0, SSE11 = 1Note) SSI11Note SCK1n Read/write trigger SOTB1n SIO1n 55H (communication data) ABH 56H ADH 5AH B5H 6AH D5H AAH CSOT1n INTCSI1n CSIIF1n SI1n (receive AAH) SO1n 55H is written to SOTB1n.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-15. Timing in 3-Wire Serial I/O Mode (2/2) (b) Transmission/reception timing (Type 2: TRMD1n = 1, DIR1n = 0, CKP1n = 0, DAP1n = 1, SSE11 = 1Note) SSI11Note SCK1n Read/write trigger 55H (communication data) SOTB1n SIO1n ABH 56H ADH 5AH B5H 6AH D5H AAH CSOT1n INTCSI1n CSIIF1n SI1n (input AAH) SO1n 55H is written to SOTB1n.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-16.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (3) Timing of output to SO1n pin (first bit) When communication is started, the value of transmit buffer register 1n (SOTB1n) is output from the SO1n pin. The output operation of the first bit at this time is described below. Figure 16-17.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-17.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (4) Output value of SO1n pin (last bit) After communication has been completed, the SO1n pin holds the output value of the last bit. Figure 16-18. Output Value of SO1n Pin (Last Bit) (1/2) (a) Type 1: CKP1n = 0, DAP1n = 0 SCK1n ( ← Next request is issued.) Writing to SOTB1n or reading from SIO1n SOTB1n SIO1n Output latch Last bit SO1n (b) Type 3: CKP1n = 1, DAP1n = 0 SCK1n Writing to SOTB1n or reading from SIO1n ( ← Next request is issued.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 Figure 16-18. Output Value of SO1n Pin (Last Bit) (2/2) (c) Type 2: CKP1n = 0, DAP1n = 1 SCK1n Writing to SOTB1n or reading from SIO1n ( ← Next request is issued.) SOTB1n SIO1n Output latch SO1n Last bit (d) Type 4: CKP1n = 1, DAP1n = 1 SCK1n Writing to SOTB1n or reading from SIO1n ( ← Next request is issued.
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78K0/Kx2-L CHAPTER 16 SERIAL INTERFACES CSI10 AND CSI11 (5) SO1n output (refer to Figures 16-1 to 16-3) The status of the SO1n output is as follows depending on the setting of CSIE1n, TRMD1n, DAP1n, and DIR1n. Table 16-3. SO1n Output Status CSIE1n CSIE1n = 0 Note 2 TRMD1n TRMD1n = 0 Note 2 TRMD1n = 1 Note 3 DIR1n − − Low level output − Low level output DAP1n = 0 DAP1n = 1 DIR1n = 0 DIR1n = 1 CSIE1n = 1 Notes 1.
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78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS CHAPTER 17 INTERRUPT FUNCTIONS 78K0/KY2-L 78K0/KA2-L 78K0/KB2-L 78K0/KC2-L (μPD78F055x) (μPD78F056x) (μPD78F057x) (μPD78F058x) Item 16 pins 20 pins 25, 32 pins 30 pins 40 pins 44 pins 48 pins Maskable External 2 4 5 8 10 11 13 interrupts Internal 10 11 13 16 16 16 10 17.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control.
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78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Table 17-1.
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78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Table 17-1.
PAGE 608
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-1.
PAGE 609
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-1.
PAGE 610
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS 17.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions.
PAGE 611
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Table 17-2.
PAGE 612
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered.
PAGE 613
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-2.
PAGE 614
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-3.
PAGE 615
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-4.
PAGE 616
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-5.
PAGE 617
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-6.
PAGE 618
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-7.
PAGE 619
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-8.
PAGE 620
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, MK1L, and MK1H are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H, and MK1L and MK1H are combined to form 16-bit registers MK0 and MK1, they are set by a 16-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 17-9.
PAGE 621
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-10.
PAGE 622
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-11.
PAGE 623
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-12.
PAGE 624
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-13.
PAGE 625
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-14.
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78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-15.
PAGE 627
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H, and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set by a 16-bit memory manipulation instruction. Reset signal generation sets these registers to FFH.
PAGE 628
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-17.
PAGE 629
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-18.
PAGE 630
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-19.
PAGE 631
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-20.
PAGE 632
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-21.
PAGE 633
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-22.
PAGE 634
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-23.
PAGE 635
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-23.
PAGE 636
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-23.
PAGE 637
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-23.
PAGE 638
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-23.
PAGE 639
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Table 17-3 shows the ports corresponding to EGPn and EGNn. Table 17-3.
PAGE 640
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Table 17-3.
PAGE 641
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Table 17-3.
PAGE 642
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW. Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated instructions (EI and DI).
PAGE 643
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS 17.4 Interrupt Servicing Operations 17.4.1 Maskable interrupt acknowledgment A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
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78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-25.
PAGE 645
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-26. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks CPU processing Instruction Instruction PSW and PC saved, jump to interrupt servicing Interrupt servicing program ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/fCPU (fCPU: CPU clock) Figure 17-27.
PAGE 646
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS 17.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0).
PAGE 647
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-28. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing IE = 0 EI IE = 0 IE = 0 EI INTxx (PR = 1) INTzz servicing EI INTyy (PR = 0) INTzz (PR = 0) RETI IE = 1 IE = 1 RETI RETI IE = 1 During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt servicing takes place.
PAGE 648
78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-28. Examples of Multiple Interrupt Servicing (2/2) Example 3.
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78K0/Kx2-L CHAPTER 17 INTERRUPT FUNCTIONS 17.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below. • MOV PSW, #byte • MOV A, PSW • MOV PSW, A • MOV1 PSW. bit, CY • MOV1 CY, PSW. bit • AND1 CY, PSW. bit • OR1 CY, PSW. bit • XOR1 CY, PSW.
PAGE 650
78K0/Kx2-L CHAPTER 18 KEY INTERRUPT FUNCTION CHAPTER 18 KEY INTERRUPT FUNCTION Item 78K0/KY2-L 78K0/KA2-L 78K0/KB2-L 78K0/KC2-L (μPD78F055x) (μPD78F056x) (μPD78F057x) (μPD78F058x) 16 pins 20, 25 32 pins 30 pins − Key interrupt 40, 44 pins 4 ch 48 pins 6 ch 18.1 Functions of Key Interrupt A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a falling edge to the key interrupt input pins (KRn). Table 18-1.
PAGE 651
78K0/Kx2-L CHAPTER 18 KEY INTERRUPT FUNCTION 18.2 Configuration of Key Interrupt The key interrupt includes the following hardware. Table 18-2. Configuration of Key Interrupt Item Control register Configuration Key return mode register (KRM) Figure 18-1.
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78K0/Kx2-L CHAPTER 18 KEY INTERRUPT FUNCTION 18.3 Register Controlling Key Interrupt (1) Key return mode register (KRM) This register controls the KRMn bit using the KRn signal. KRM is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears KRM to 00H. Figure 18-2.
PAGE 653
78K0/Kx2-L CHAPTER 19 STANDBY FUNCTION CHAPTER 19 STANDBY FUNCTION 19.1 Standby Function and Configuration 19.1.1 Standby function The standby function is mounted onto all 78K0/Kx2-L microcontroller products. The standby function is designed to reduce the operating current of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped.
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78K0/Kx2-L CHAPTER 19 STANDBY FUNCTION 19.1.2 Registers controlling standby function The standby function is controlled by the following two registers. • Oscillation stabilization time counter status register (OSTC) • Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, refer to CHAPTER 5 CLOCK GENERATOR.
PAGE 655
78K0/Kx2-L CHAPTER 19 STANDBY FUNCTION Figure 19-1. Format of Oscillation Stabilization Time Counter Status Register (OSTC) Address: FFA3H After reset: 00H R Symbol 7 6 5 4 3 2 1 0 OSTC 0 0 0 MOST11 MOST13 MOST14 MOST15 MOST16 MOST11 MOST13 MOST14 MOST15 MOST16 Oscillation stabilization time status fX = 10 MHz 11 204.8 μs min. 13 819.2 μs min. 14 1.64 ms min. 15 3.27 ms min. 16 6.55 ms min. 1 0 0 0 0 2 /fX min. 1 1 0 0 0 2 /fX min.
PAGE 656
78K0/Kx2-L CHAPTER 19 STANDBY FUNCTION Figure 19-2. Format of Oscillation Stabilization Time Select Register (OSTS) Address: FFA4H After reset: 05H R/W Symbol 7 6 5 4 3 2 1 0 OSTS 0 0 0 0 0 OSTS2 OSTS1 OSTS0 OSTS2 OSTS1 OSTS0 Oscillation stabilization time selection fX = 10 MHz 0 0 0 1 1 0 1 1 1.64 ms 15 3.27 ms 16 6.55 ms 2 /fX 0 0 819.2 μs 14 2 /fX 1 0 204.8 μs 13 2 /fX 0 1 11 2 /fX 1 2 /fX Other than above Setting prohibited Cautions 1.
PAGE 657
78K0/Kx2-L CHAPTER 19 STANDBY FUNCTION Table 19-1.
PAGE 658
78K0/Kx2-L CHAPTER 19 STANDBY FUNCTION Table 19-1.
PAGE 659
78K0/Kx2-L CHAPTER 19 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 19-3.
PAGE 660
78K0/Kx2-L CHAPTER 19 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 19-4.
PAGE 661
78K0/Kx2-L CHAPTER 19 STANDBY FUNCTION Figure 19-4.
PAGE 662
78K0/Kx2-L CHAPTER 19 STANDBY FUNCTION Table 19-3.
PAGE 663
78K0/Kx2-L CHAPTER 19 STANDBY FUNCTION Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware. 2. When transitioning to the STOP mode, it is possible to achieve low power consumption by setting RMC = 56H. 3.
PAGE 664
78K0/Kx2-L CHAPTER 19 STANDBY FUNCTION (2) STOP mode release Figure 19-5.
PAGE 665
78K0/Kx2-L CHAPTER 19 STANDBY FUNCTION Figure 19-6.
PAGE 666
78K0/Kx2-L CHAPTER 19 STANDBY FUNCTION Figure 19-6.
PAGE 667
78K0/Kx2-L CHAPTER 19 STANDBY FUNCTION Figure 19-7.
PAGE 668
78K0/Kx2-L CHAPTER 19 STANDBY FUNCTION Table 19-4. Operation in Response to Interrupt Request in STOP Mode Release Source Maskable interrupt MK×× PR×× IE ISP 0 0 0 × request Operation Next address instruction execution 0 0 1 × Interrupt servicing execution 0 1 0 1 Next address 0 1 × 0 instruction execution 0 1 1 1 Interrupt servicing execution Reset 1 × × × STOP mode held − − × × Reset processing ×: don’t care R01UH0028EJ0400 Rev.4.
PAGE 669
78K0/Kx2-L CHAPTER 20 RESET FUNCTION CHAPTER 20 RESET FUNCTION The reset function is mounted onto all 78K0/Kx2-L microcontroller products. The following four operations are available to generate a reset signal.
PAGE 670
78K0/Kx2-L R01UH0028EJ0400 Rev.4.00 Sep 27, 2010 Figure 20-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF LVIRF Set Set Watchdog timer reset signal Clear Clear RESF register read signal RESET Reset signal to LVIM/LVIS register Power-on-clear circuit reset signal Caution An LVI circuit internal reset does not reset the LVI circuit. Remarks 1. LVIM: Low-voltage detection register 2.
PAGE 671
78K0/Kx2-L CHAPTER 20 RESET FUNCTION Figure 20-2. Timing of Reset by RESET Input Wait for oscillation accuracy stabilization (102 to 407 μs) Internal high-speed oscillation clock Starting X1 oscillation is specified by software.
PAGE 672
78K0/Kx2-L CHAPTER 20 RESET FUNCTION Figure 20-4. Timing of Reset in STOP Mode by RESET Input STOP instruction execution Wait for oscillation accuracy stabilization (102 to 407 μs) Internal high-speed oscillation clock Starting X1 oscillation is specified by software.
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78K0/Kx2-L CHAPTER 20 RESET FUNCTION Table 20-1. Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped.
PAGE 674
78K0/Kx2-L CHAPTER 20 RESET FUNCTION Table 20-2. Hardware Statuses After Reset Acknowledgment (1/4) Hardware After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set.
PAGE 675
78K0/Kx2-L CHAPTER 20 RESET FUNCTION Table 20-2.
PAGE 676
78K0/Kx2-L CHAPTER 20 RESET FUNCTION Table 20-2.
PAGE 677
78K0/Kx2-L CHAPTER 20 RESET FUNCTION Table 20-2.
PAGE 678
78K0/Kx2-L CHAPTER 20 RESET FUNCTION 20.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/Kx2-L microcontrollers. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset by power-on-clear (POC) circuit, and reading RESF set RESF to 00H. Figure 20-5.
PAGE 679
78K0/Kx2-L CHAPTER 21 POWER-ON-CLEAR CIRCUIT CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) is mounted onto all 78K0/Kx2-L microcontroller products. The power-on-clear circuit has the following functions. • Generates internal reset signal at power on. • The reset signal is released when the supply voltage (VDD) exceeds POC detection voltage (VPOR = 1.61 V ±0.09 V).
PAGE 680
78K0/Kx2-L CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 21-1. Figure 21-1. Block Diagram of Power-on-Clear Circuit VDD VDD + Internal reset signal − Reference voltage source 21.3 Operation of Power-on-Clear Circuit • An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds POC detection voltage (VPOR = 1.61 V ±0.09 V), the reset status is released.
PAGE 681
78K0/Kx2-L CHAPTER 21 POWER-ON-CLEAR CIRCUIT Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (1/2) (1) When LVI is OFF upon power application (option byte: LVISTART = 0) Set LVI to be used for reset Set LVI to be used for interrupt Set LVI to be used for reset Supply voltage (VDD) VLVI 1.8 VNote 1 VPOR = 1.61 V (TYP.) VPDR = 1.59 V (TYP.) 0.5 V/ms (MIN.
PAGE 682
78K0/Kx2-L CHAPTER 21 POWER-ON-CLEAR CIRCUIT Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (2/2) (2) When LVI is ON upon power application (option byte: LVISTART = 1) Set LVI to be used for interrupt Set LVI to be used for reset Set LVI to be used for reset Supply voltage (VDD) VLVI VLVI = 1.91 V (TYP.) 1.8 VNote 1 VPOR = 1.61 V (TYP.) VPDR = 1.59 V (TYP.
PAGE 683
78K0/Kx2-L CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage (VPOR, VPDR), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
PAGE 684
78K0/Kx2-L CHAPTER 21 POWER-ON-CLEAR CIRCUIT Figure 21-3. Example of Software Processing After Reset Release (2/2) • Checking reset source Check reset source WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer LVIRF of RESF register = 1? Yes No Reset processing by low-voltage detector Power-on-clear/external reset generated R01UH0028EJ0400 Rev.4.
PAGE 685
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR CHAPTER 22 LOW-VOLTAGE DETECTOR 22.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) is mounted onto all 78K0/Kx2-L microcontroller products. The low-voltage detector has the following functions. • The LVI circuit compares the supply voltage (VDD) with the LVI detection voltage (VLVI) or the input voltage from an external input pin (EXLVI) with the LVI detection voltage (VEXLVI = 1.21 V ±0.
PAGE 686
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR 22.2 Configuration of Low-Voltage Detector The block diagram of the low-voltage detector is shown in Figure 22-1. Figure 22-1.
PAGE 687
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-2.
PAGE 688
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR Cautions 1. To stop LVI, follow either of the procedures below. • When using 8-bit memory manipulation instruction: Write 00H to LVIM. • When using 1-bit memory manipulation instruction: Clear LVION to 0. 2. Input voltage from external input pin (EXLVI) must be EXLVI < VDD. 3.
PAGE 689
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level select register (LVIS) This register selects the low-voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation input sets this register to 00H. Figure 22-3.
PAGE 690
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR (3) Port mode register 12 (PM12) (78K0/KB2-L and 78K0/KC2-L only) When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this time, the output latch of P120 may be 0 or 1. PM12 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 22-4.
PAGE 691
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR (2) Used as interrupt (LVIMD = 0) • If LVISEL = 0, compares the supply voltage (VDD) and LVI detection voltage (VLVI). When VDD drops lower than VLVI (VDD < VLVI) or when VDD becomes VLVI or higher (VDD ≥ VLVI), generates an interrupt signal (INTLVI). • If LVISEL = 1, compares the input voltage from external input pin (EXLVI) and LVI detection voltage (VEXLVI = 1.21 V ±0.1 V).
PAGE 692
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR 22.4.1 When used as reset (1) When detecting level of supply voltage (VDD) (a) When LVI default start function stopped is set (LVISTART = 0) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1).
PAGE 693
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Bit: LVISEL = 0, Option Byte: LVISTART = 0) Set LVI to be used for reset Supply voltage (VDD) VLVI VPOR = 1.61 V (TYP.) VPDR = 1.59 V (TYP.
PAGE 694
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR (b) When LVI default start function enabled is set (LVISTART = 1) The setting when operation starts and when operation stops is the same as that described in 22.4.1 (1) When LVI default start function stopped is set (LVISTART = 0). Figure 22-6. Timing of Low-Voltage Detector Internal Reset Signal Generation (Bit: LVISEL = 0, Option Byte: LVISTART = 1) Set LVI to be used for reset Supply voltage (VDD) VLVI VLVI = 1.91 V (TYP.) VPOR = 1.61 V (TYP.
PAGE 695
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR (2) When detecting level of input voltage from external input pin (EXLVI) (78K0/KB2-L and 78K0/KC2-L only) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)). <3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <4> Use software to wait for an operation stabilization time (10 μs (MAX.)).
PAGE 696
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-7.
PAGE 697
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR 22.4.2 When used as interrupt (1) When detecting level of supply voltage (VDD) (a) When LVI default start function stopped is set (LVISTART = 0) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1).
PAGE 698
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-8. Timing of Low-Voltage Detector Interrupt Signal Generation (Bit: LVISEL = 0, Option Byte: LVISTART = 0) Supply voltage (VDD) VLVI VPOR = 1.61 V (TYP.) VPDR = 1.59 V (TYP.
PAGE 699
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR (b) When LVI default start function enabled is set (LVISTART = 1) The setting when operation starts and when operation stops is the same as that described in 22.4.2 (1) When LVI default start function stopped is set (LVISTART = 0). Figure 22-9. Timing of Low-Voltage Detector Interrupt Signal Generation (Bit: LVISEL = 0, Option Byte: LVISTART = 1) Supply voltage (VDD) VLVI VLVI = 1.91 V (TYP.) VPOR = 1.61 V (TYP.) VPDR = 1.59 V (TYP.
PAGE 700
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR (2) When detecting level of input voltage from external input pin (EXLVI) (78K0/KB2-L and 78K0/KC2-L only) • When starting operation <1> <2> Mask the LVI interrupt (LVIMK = 1). Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)). <3> Clear bit 1 (LVIMD) of LVIM to 0 (generates interrupt signal when the level is detected) (default value).
PAGE 701
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-10. Timing of Low-Voltage Detector Interrupt Signal Generation (Bit: LVISEL = 1) Input voltage from external input pin (EXLVI) VEXLVI Note 3 LVIMK flag (set by software) Note 3 Time <1> Note 1 <8> Cleared by software LVISEL flag (set by software) <2> LVION flag (set by software) <4> <5> Wait time LVIF flag <6> Note 2 INTLVI Note 2 LVIIF flag Note 2 LVIMD flag (set by software) <7> Cleared by software L <3> Notes 1.
PAGE 702
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR 22.5 Cautions for Low-Voltage Detector In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. Operation example 1: When used as reset The system may be repeatedly reset and released from the reset status.
PAGE 703
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-11. Example of Software Processing After Reset Release (1/2) • If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset ; Check the reset sourceNote Initialization processing <1> LVI reset ; Setting of detection level by LVIS. The low-voltage detector operates (LVION = 1).
PAGE 704
78K0/Kx2-L CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-11. Example of Software Processing After Reset Release (2/2) • Checking reset source Check reset source WDTRF of RESF register = 1? Yes No Reset processing by watchdog timer LVIRF of RESF register = 1? No Yes Power-on-clear/external reset generated Reset processing by low-voltage detector Operation example 2: When used as interrupt Interrupt requests may be generated frequently. Take the following action.
PAGE 705
78K0/Kx2-L CHAPTER 23 REGULATOR CHAPTER 23 REGULATOR 23.1 Regulator Overview The 78K0/Kx2-L microcontrollers contain a circuit for operating the device with a constant voltage. At this time, in order to stabilize the regulator output voltage, connect the REGC pin to VSS via a capacitor (0.47 to 1 μF). However, when using the STOP mode that has been entered since operation of the internal high-speed oscillation clock and external main system clock, 0.47 μF is recommended.
PAGE 706
78K0/Kx2-L CHAPTER 23 REGULATOR 23.3 Cautions for Self Programming 1. Make sure that the regulator output voltage mode is fixed when executing self programming or EEPROM emulation. 2. The power supply voltage range in which the flash memory can be rewritten in normal power mode is VDD ≥ 2.5 V. Note that program area can be rewritten by using the self programming library in normal power mode. 3.
PAGE 707
78K0/Kx2-L CHAPTER 24 OPTION BYTE CHAPTER 24 OPTION BYTE 24.1 Functions of Option Bytes The flash memory at 0080H to 0084H of the 78K0/Kx2-L microcontrollers is an option byte area. When power is turned on or when the device is restarted from the reset status, the device automatically references the option bytes and sets specified functions. When using the product, be sure to set the following functions by using the option bytes.
PAGE 708
78K0/Kx2-L CHAPTER 24 OPTION BYTE (3) 0082H/1082H { Internal high-speed oscillation clock frequency selection • 4 MHz (TYP.) • 8 MHz (TYP.) Caution Set a value that is the same as that of 0082H to 1082H because 0082H and 1082H are switched during the boot swap operation.
PAGE 709
78K0/Kx2-L CHAPTER 24 OPTION BYTE Figure 24-1.
PAGE 710
78K0/Kx2-L CHAPTER 24 OPTION BYTE Figure 24-1. Format of Option Byte (2/3) Notes 1, 2 Address: 0081H/1081H 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 LVISTART LVISTART Notes 1. LVI default start operation control 0 LVI is OFF by default upon power application (LVI default start function stopped) 1 LVI is ON by default upon power application (LVI default start function enabled) LVISTART can only be written by using a dedicated flash memory programmer.
PAGE 711
78K0/Kx2-L CHAPTER 24 OPTION BYTE Figure 24-1. Format of Option Byte (3/3) Note Address: 0083H/1083H 7 6 5 4 3 2 1 0 0 0 0 1 1 1 OCDPSEL 0 OCDPSEL Pin selection used during on-chip debugging 0 TOOLC1/P31, TOOLD1/P32 1 TOOLC0/X1, TOOLD0/X2 Note Set a value that is the same as that of 0083H to 1083H because 0083H and 1083H are switched during the boot swap operation. Cautions 1. Be sure to clear bits 7 to 5 and 0 to “0” and set bits 4 to 2 to “1”. 2.
PAGE 712
78K0/Kx2-L CHAPTER 24 OPTION BYTE Here is an example of description of the software for setting the option bytes. OPT CSEG OPTION: DB AT 0080H 30H ; Enables watchdog timer operation (illegal access detection operation), ; Window open period of watchdog timer: 50%, ; Overflow time of watchdog timer: 27/fIL, ; Internal low-speed oscillator can be stopped by software. DB 00H ; LVI default start function stopped DB 00H ; Internal high-speed oscillation clock frequency 8 MHz (TYP.
PAGE 713
78K0/Kx2-L CHAPTER 25 FLASH MEMORY CHAPTER 25 FLASH MEMORY The 78K0/Kx2-L microcontrollers incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. 25.1 Internal Memory Size Switching Register Select the internal memory capacity using the internal memory size switching register (IMS). IMS is set by an 8-bit memory manipulation instruction. Reset signal generation sets IMS to CFH.
PAGE 714
78K0/Kx2-L CHAPTER 25 FLASH MEMORY Table 25-1. Set Values of Internal Memory Size Switching Register Products IMS Setting 78K0/KY2-L 78K0/KA2-L 78K0/KB2-L 78K0/KC2-L μPD78F0550, μPD78F0560, 78F0555 78F0565 − − μPD78F0551, μPD78F0561, μPD78F0571, μPD78F0581, 78F0556 78F0566 78F0576 78F0586 μPD78F0552, μPD78F0562, μPD78F0572, μPD78F0582, 78F0557 78F0567 78F0577 78F0587 − − μPD78F0573, μPD78F0583, 78F0578 78F0588 61H 42H 04H C8H 25.
PAGE 715
78K0/Kx2-L CHAPTER 25 FLASH MEMORY 25.3 Programming Environment The environment required for writing a program to the flash memory of the 78K0/Kx2-L microcontrollers are illustrated below. Figure 25-2.
PAGE 716
78K0/Kx2-L CHAPTER 25 FLASH MEMORY 25.4 Connection of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset.
PAGE 717
78K0/Kx2-L CHAPTER 25 FLASH MEMORY 25.4.2 RESET pin If the reset signal of the dedicated flash memory programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator. If the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed.
PAGE 718
78K0/Kx2-L CHAPTER 25 FLASH MEMORY 25.4.7 On-board writing when connecting crystal/ceramic resonator To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset.
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78K0/Kx2-L CHAPTER 25 FLASH MEMORY 25.5 Programming Method 25.5.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 25-6. Flash Memory Manipulation Procedure Start Flash memory programming mode is set Manipulate flash memory End? No Yes End 25.5.2 Flash memory programming mode To rewrite the contents of the flash memory by using the dedicated flash memory programmer, set the 78K0/Kx2-L microcontrollers in the flash memory programming mode.
PAGE 720
78K0/Kx2-L CHAPTER 25 FLASH MEMORY Table 25-5. Flash Memory Control Commands Classification Verify Command Name Function Compares the contents of a specified area of the flash memory with Verify data transmitted from the programmer. Erase Blank check Chip Erase Erases the entire flash memory. Block Erase Erases a specified area in the flash memory. Block Blank Check Checks if a specified block in the flash memory has been correctly erased.
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78K0/Kx2-L CHAPTER 25 FLASH MEMORY 25.6 Security Settings The 78K0/Kx2-L microcontrollers support a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed using the Security Set command. The security setting is valid when the programming mode is set next.
PAGE 722
78K0/Kx2-L CHAPTER 25 FLASH MEMORY Table 25-7. Relationship Between Enabling Security Function and Command (1) During on-board/off-board programming Valid Security Executed Command Batch Erase (Chip Erase) Prohibition of batch erase (chip erase) Prohibition of block erase Block Erase Write Note Cannot be erased in batch Blocks cannot be Can be performed Can be erased in batch. erased. Can be performed. Prohibition of writing . Cannot be performed.
PAGE 723
78K0/Kx2-L CHAPTER 25 FLASH MEMORY 25.7 Processing Time for Each Command When PG-FP5 Is Used (Reference) The following table shows the processing time for each command (reference) when the PG-FP5 is used as a dedicated flash memory programmer. Table 25-9.
PAGE 724
78K0/Kx2-L CHAPTER 25 FLASH MEMORY Table 25-9. Processing Time for Each Command When PG-FP5 Is Used (Reference) (2/3) (1) 78K0/KY2-L, 78K0/KA2-L (2/2) (c) Products with internal ROMs of the 16 KB: μPD78F0552, 78F0557, 78F0562, 78F0567 Command of PG-FP5 Port: UART-Internal-OSC (Internal high-speed oscillation clock (fIH: 8 MHz (typ.)), Speed: 500,000 bps Signature 0.5 s (typ.) Blankcheck 0.5 s (typ.) Erase 1 s (typ.) Program 2.5 s (typ.) Verify 1.5 s (typ.) E.P.V 2.5 s (typ.
PAGE 725
78K0/Kx2-L CHAPTER 25 FLASH MEMORY Table 25-9. Processing Time for Each Command When PG-FP5 Is Used (Reference) (3/3) (2) 78K0/KB2-L, 78K0/KC2-L (2/2) (b) Products with internal ROMs of the 16 KB: μPD78F0572, 78F0577, 78F0582, 78F0587 Command of PG-FP5 Port: UART-Internal-OSC (Internal high-speed oscillation clock (fIH: 8 MHz (typ.)), Speed: 500,000 bps Signature 0.5 s (typ.) Blankcheck 1 s (typ.) Erase 1 s (typ.) Program 2.5 s (typ.) Verify 1.5 s (typ.) E.P.V 2.5 s (typ.
PAGE 726
78K0/Kx2-L CHAPTER 25 FLASH MEMORY 25.8 Flash Memory Programming by Self Programming The 78K0/Kx2-L microcontrollers support a self programming function that can be used to rewrite the flash memory via a user program. Because this function allows a user application to rewrite the flash memory by using the 78K0/Kx2-L microcontroller self programming library, it can be used to upgrade the program in the field.
PAGE 727
78K0/Kx2-L CHAPTER 25 FLASH MEMORY 25.8.1 Register controlling self programming mode The self programming mode is controlled by the self programming mode control register (FPCTL). FPCTL can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears FPCTL to 00H. Figure 25-8.
PAGE 728
78K0/Kx2-L CHAPTER 25 FLASH MEMORY Figure 25-9.
PAGE 729
78K0/Kx2-L CHAPTER 25 FLASH MEMORY 25.8.3 Boot swap function If rewriting the boot area failed by temporary power failure or other reasons, restarting a program by resetting or overwriting is disabled due to data destruction in the boot area. The boot swap function is used to avoid this problem. Before erasing boot cluster 0Note, which is a boot program area, by self programming, write a new boot program to boot cluster 1 in advance.
PAGE 730
78K0/Kx2-L CHAPTER 25 FLASH MEMORY Figure 25-11.
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78K0/Kx2-L CHAPTER 25 FLASH MEMORY 25.9 Creating ROM Code to Place Order for Previously Written Product Before placing an order with Renesas Electronics for a previously written product, the ROM code for the order must be created. To create the ROM code, use the Hex Consolidation Utility (hereafter abbreviated to HCU) on the finished programs (hex files) and optional data (such as security settings for flash memory programs).
PAGE 732
78K0/Kx2-L CHAPTER 26 ON-CHIP DEBUG FUNCTION CHAPTER 26 ON-CHIP DEBUG FUNCTION 26.1 Connecting QB-MINI2 to 78K0/Kx2-L Microcontrollers The 78K0/Kx2-L microcontrollers use the VDD, RESET, TOOLC0/X1 (or TOOLC1/P31), TOOLD0/X2 (or TOOLD1/P32), and VSS pins to communicate with the host machine via an on-chip debug emulator (QB-MINI2). Whether TOOLC0/X1 and TOOLC1/P31, or TOOLD0/X2 and TOOLD1/P32 are used can be selected. Cautions 1.
PAGE 733
78K0/Kx2-L CHAPTER 26 ON-CHIP DEBUG FUNCTION Figure 26-1. Connection Example of QB-MINI2 and 78K0/Kx2-L Microcontrollers (1/3) (1) When using the TOOLC0 and TOOLD0 pins (X1 oscillator or EXCLK input clock is not used, both debugging and programming are performed) VDD Target connector Target device 1 GND RESET_OUT VDD 3 k to 10 kΩ 2 RESETNote 1 3 RxD VDD TxD R.F.U. 4 TOOLD0(X2)Note 3 VDD 5 6 7 R.F.U. R.F.U. CLKNote 2 R.F.U. R.F.U. FLMD1 8 9 10 12 DATA Note 5 RESET_IN R.F.U.
PAGE 734
78K0/Kx2-L CHAPTER 26 ON-CHIP DEBUG FUNCTION Figure 26-1. Connection Example of QB-MINI2 and 78K0/Ix2 Microcontrollers (2/3) (2) When using the TOOLC0 and TOOLD0 pins (with X1/X2 oscillator is used, both debugging and programming are performed) VDD Target connector GND RESET_OUT RxD VDD TxD R.F.U. R.F.U. R.F.U. CLK Note 2 R.F.U. R.F.U. FLMD1 DATA FLMD0 Note 4 RESET_IN R.F.U.
PAGE 735
78K0/Kx2-L CHAPTER 26 ON-CHIP DEBUG FUNCTION Figure 26-1. Connection Example of QB-MINI2 and 78K0/Kx2-L Microcontrollers (3/3) (3) When using the TOOLC1 and TOOLD1 pins (both debugging and programming are performed) VDD Target connector Target device 3 k to 10 kΩ 1 VDD GND RESET_OUT 2 Note 1 RESET 3 RxD VDD TxD R.F.U. R.F.U. R.F.U. CLKNote 2 R.F.U. R.F.U. FLMD1 4 5 6 7 8 9 10 kΩNote 4 RESET_IN R.F.U.
PAGE 736
78K0/Kx2-L CHAPTER 26 ON-CHIP DEBUG FUNCTION Table 26-1. On-Chip Debug Security ID Address On-Chip Debug Security ID 0085H to 008EH Any ID code of 10 bytes 1085H to 108EH 26.3 Securing of User Resources QB-MINI2 uses the user memory spaces (shaded portions in Figure 26-2) to implement communication with the target device, or each debug functions. The areas marked with a dot (•) are always used for debugging, and other areas are used for each debug function used.
PAGE 737
78K0/Kx2-L CHAPTER 27 INSTRUCTION SET CHAPTER 27 INSTRUCTION SET This chapter lists each instruction set of the 78K0/Kx2-L microcontrollers in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E). 27.1 Conventions Used in Operation List 27.1.
PAGE 738
78K0/Kx2-L CHAPTER 27 INSTRUCTION SET 27.1.
PAGE 739
78K0/Kx2-L CHAPTER 27 INSTRUCTION SET 27.
PAGE 740
78K0/Kx2-L Instruction Group 16-bit data CHAPTER 27 INSTRUCTION SET Mnemonic MOVW transfer Operands Note 1 Note 2 6 − rp ← word saddrp, #word 4 8 10 (saddrp) ← word sfrp, #word 4 − 10 sfrp ← word AX, saddrp 2 6 8 AX ← (saddrp) saddrp, AX 2 6 8 (saddrp) ← AX AX, sfrp 2 − 8 AX ← sfrp 2 − 8 sfrp ← AX AX, rp Note 3 1 4 − AX ← rp rp, AX Note 3 1 4 − rp ← AX AX, !addr16 3 10 12 AX ← (addr16) !addr16, AX 3 10 12 (addr16) ← AX 1 4 − AX ↔ rp XCHW AX,
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78K0/Kx2-L Instruction Group 8-bit CHAPTER 27 INSTRUCTION SET Mnemonic SUB operation Operands A, #byte saddr, #byte A, r Note 3 r, A SUBC Z AC CY Note 1 Note 2 2 4 − A, CY ← A − byte × × × 3 6 8 (saddr), CY ← (saddr) − byte × × × 2 4 − A, CY ← A − r × × × 2 4 − r, CY ← r − A × × × 2 4 5 A, CY ← A − (saddr) × × × A, !addr16 3 8 9 A, CY ← A − (addr16) × × × A, [HL] 1 4 5 A, CY ← A − (HL) × × × A, [HL + byte] 2 8 9 A, CY ← A − (HL + byte) × ×
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78K0/Kx2-L Instruction Group 8-bit CHAPTER 27 INSTRUCTION SET Mnemonic OR Operands A, #byte operation saddr, #byte A, r Note 3 r, A XOR Z AC CY Note 1 Note 2 2 4 − A ← A ∨ byte 3 6 8 (saddr) ← (saddr) ∨ byte × 2 4 − A←A∨r × 2 4 − r←r∨A × × 2 4 5 A ← A ∨ (saddr) × A, !addr16 3 8 9 A ← A ∨ (addr16) × A, [HL] 1 4 5 A ← A ∨ (HL) × A, [HL + byte] 2 8 9 A ← A ∨ (HL + byte) × A, [HL + B] 2 8 9 A ← A ∨ (HL + B) × A, [HL + C] 2 8 9 A ← A ∨ (HL + C) ×
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78K0/Kx2-L Instruction Group CHAPTER 27 INSTRUCTION SET Mnemonic Operands Clocks Bytes Flag Operation Z AC CY Note 1 Note 2 16-bit ADDW AX, #word 3 6 − AX, CY ← AX + word × × × operation SUBW AX, #word 3 6 − AX, CY ← AX − word × × × CMPW AX, #word 3 6 − AX − word × × × MULU X 2 16 − AX ← A × X divide DIVUW C 2 25 − AX (Quotient), C (Remainder) ← AX ÷ C Increment/ INC r 1 2 − r←r+1 × × saddr 2 4 6 (saddr) ← (saddr) + 1 × × Multiply/ decre
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78K0/Kx2-L Instruction Group Bit CHAPTER 27 INSTRUCTION SET Mnemonic AND1 manipulate OR1 XOR1 SET1 CLR1 Notes 1. 2. Operands CY, saddr.bit Clocks Bytes 3 Flag Operation Z AC CY Note 1 Note 2 6 7 CY ← CY ∧ (saddr.bit) × CY, sfr.bit 3 − 7 CY ← CY ∧ sfr.bit × CY, A.bit 2 4 − CY ← CY ∧ A.bit × CY, PSW.bit 3 − 7 CY ← CY ∧ PSW.bit × CY, [HL].bit 2 6 7 CY ← CY ∧ (HL).bit × CY, saddr.bit 3 6 7 CY ← CY ∨ (saddr.bit) × CY, sfr.bit 3 − 7 CY ← CY ∨ sfr.
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78K0/Kx2-L Instruction Group Call/return CHAPTER 27 INSTRUCTION SET Mnemonic CALL Operands !addr16 Clocks Bytes 3 Operation Note 1 Note 2 7 − Flag Z AC CY (SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L, PC ← addr16, SP ← SP − 2 CALLF !addr11 2 5 − (SP − 1) ← (PC + 2)H, (SP − 2) ← (PC + 2)L, PC15 − 11 ← 00001, PC10 − 0 ← addr11, SP ← SP − 2 CALLT [addr5] 1 6 − (SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L, PCH ← (addr5 + 1), PCL ← (addr5), SP ← SP − 2 BRK 1 6 − (SP − 1) ← PSW, (SP − 2)
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78K0/Kx2-L Instruction Group CHAPTER 27 INSTRUCTION SET Mnemonic Operands Note 2 8 9 PC ← PC + 3 + jdisp8 if (saddr.bit) = 1 sfr.bit, $addr16 4 − 11 PC ← PC + 4 + jdisp8 if sfr.bit = 1 A.bit, $addr16 3 8 − PC ← PC + 3 + jdisp8 if A.bit = 1 PSW.bit, $addr16 3 − 9 PC ← PC + 3 + jdisp8 if PSW.bit = 1 [HL].bit, $addr16 3 10 11 PC ← PC + 3 + jdisp8 if (HL).bit = 1 saddr.bit, $addr16 4 10 11 PC ← PC + 4 + jdisp8 if (saddr.bit) = 0 sfr.
PAGE 747
78K0/Kx2-L CHAPTER 27 INSTRUCTION SET 27.
PAGE 748
78K0/Kx2-L CHAPTER 27 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand #word AX rp Note sfrp saddrp !addr16 SP None First Operand AX ADDW MOVW SUBW XCHW MOVW MOVW MOVW MOVW CMPW rp MOVW MOVW Note INCW DECW PUSH POP sfrp MOVW MOVW saddrp MOVW MOVW !addr16 SP MOVW MOVW MOVW Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand A.
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78K0/Kx2-L CHAPTER 27 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand AX !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP R01UH0028EJ0400 Rev.4.
PAGE 750
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS CHAPTER 28 ELECTRICAL SPECIFICATIONS Target products: 78K0/KY2-L: μPD78F0550, 78F0551, 78F0552, 78F0555, 78F0556, 78F0557 78K0/KA2-L: μPD78F0560, 78F0561, 78F0562, 78F0565, 78F0566, 78F0567 78K0/KB2-L: μPD78F0571, 78F0572, 78F0573, 78F0576, 78F0577, 78F0578 78K0/KC2-L: μPD78F0581, 78F0582, 78F0583, 78F0586, 78F0587, 78F0588 Cautions 1. The 78K0/Kx2-L microcontrollers have an on-chip debug function, which is provided for development and evaluation.
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78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS (2) Non-port functions Port 78K0/KY2-L 78K0/KA2-L 16 Pins Power supply, 20 Pins 78K0/KB2-L 25 Pins 32 Pins VDD, VSS, AVREF 30 Pins 78K0/KC2-L 40 Pins 44 Pins 48 Pins VDD, VSS, AVREF, AVSS ground Regulator REGC Reset RESET Clock X1, X2, EXCLK X1, X2, EXCLK, XT1, XT2, EXCLKS oscillation Interrupt Key interrupt TM00 INTP0, INTP0 to INTP1 INTP3 INTP0, INTP2 to INTP5 INTP0 to INTP0 to INTP0 to INTP0 to INTP5, INTP5, INTP5, I
PAGE 752
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Absolute Maximum Ratings (TA = 25°C) (78K0/KY2-L, 78K0/KA2-L (20 pins), 78K0/KB2-L, 78K0/KC2-L) (1/2) Parameter Symbol Supply voltage Conditions Ratings Unit VDD −0.5 to +6.5 V VSS −0.5 to +0.3 −0.5 to VDD + 0.3 AVREF AVSS REGC pin input voltage Note 2 V VIREGC Note 1 V −0.5 to +0.3 V –0.5 to +3.6 V and –0.5 to VDD +0.
PAGE 753
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Absolute Maximum Ratings (TA = 25°C) (78K0/KY2-L, 78K0/KA2-L (20 pins), 78K0/KB2-L, 78K0/KC2-L) (2/2) Parameter Output current, high Symbol Ratings Unit −10 mA −25 mA −55 mA −0.
PAGE 754
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Absolute Maximum Ratings (TA = 25°C) (78K0/KA2-L (25 pins, 32 pins)) Parameter Symbol Supply voltage Conditions Ratings Unit VDD −0.5 to +6.5 V VSS −0.5 to +0.3 −0.5 to VDD + 0.3 AVREF AVSS REGC pin input voltage Note 2 V VIREGC Note 1 V −0.5 to +0.3 V –0.5 to +3.6 V and –0.5 to VDD +0.
PAGE 755
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. X1 Oscillator Characteristics (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V) Resonator Recommended Circuit Ceramic resonator, X1 clock VSS X1 X2 Conditions MIN. TYP. MAX. Unit MHz 2.7 V ≤ VDD ≤ 5.5 V 1.0 10.0 1.8 V ≤ VDD < 2.7 V 1.0 5.
PAGE 756
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Internal High-speed Oscillator Characteristics (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V) Resonator Parameter Conditions MIN. TYP. MAX.
PAGE 757
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. XT1 Oscillator Characteristics (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V) Resonator Crystal resonator Recommended Circuit VSS XT2 XT1 XT1 clock oscillation Conditions AMPHXT = 0 MIN. TYP. MAX. Unit 32 32.768 35 kHz Note frequency (fXT) Rd C4 Parameter C3 Note Indicates only oscillator characteristics.
PAGE 758
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (1/8) (78K0/KY2-L, 78K0/KA2-L (20 pins), 78K0/KB2-L, 78K0/KC2-L) (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, AVREF ≤ VDD, VSS = AVSS = 0 V) Parameter Symbol Note 1 Output current, high Conditions Note 2 TYP. MAX. Unit Per pin for P00 to P02, P10 to P17, P30 to P33, P40 to P42, P60 to P63, P70 to P75, P120 4.0 V ≤ VDD ≤ 5.5 V −3.
PAGE 759
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (2/8) (78K0/KY2-L, 78K0/KA2-L (20 pins), 78K0/KB2-L, 78K0/KC2-L) (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.
PAGE 760
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (3/8) (78K0/KY2-L, 78K0/KA2-L (20 pins), 78K0/KB2-L, 78K0/KC2-L) (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, AVREF ≤ VDD, VSS = AVSS = 0 V) Parameter Output voltage, low Input leakage current, Symbol VOL1 Conditions P00 to P02, P10 to P17, P30 to P33, P40 to P42, P70 to P75, P120 MIN. TYP. MAX. Unit 4.0 V ≤ VDD ≤ 5.5 V, IOL1 = 8.
PAGE 761
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (4/8) (78K0/KA2-L (25 pins, 32 pins)) (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, AVREF ≤ VDD, VSS = AVSS = 0 V) Parameter Symbol Note 1 Output current, high IOH1 Conditions MAX. Unit 4.0 V ≤ VDD ≤ 5.5 V −3.0 mA 2.7 V ≤ VDD < 4.0 V −2.5 mA 1.8 V ≤ VDD < 2.7 V −1.0 mA Total of P02, P60, P61 4.0 V ≤ VDD ≤ 5.5 V −9.0 mA 2.
PAGE 762
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (5/8) (78K0/KA2-L (25 pins, 32 pins)) (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, AVREF ≤ VDD, VSS = AVSS = 0 V) Parameter Input voltage, high Symbol Conditions VIH1 P122, P37 VIH2 P20 to P27, P70 to P72 VIH3 P60, P61, P121, P125 (I/O port mode) VIH4 P00 to P02, P31 to P36, RESET, EXCLK VIH5 P60, P61 AVREF = VDD 2.
PAGE 763
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (6/8) (78K0/KA2-L (25 pins, 32 pins)) (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, AVREF ≤ VDD, VSS = AVSS = 0 V) Parameter Output voltage, low Input leakage current, Symbol VOL1 Conditions P00 to P02, P31 to P37 TYP. MAX. Unit 4.0 V ≤ VDD ≤ 5.5 V, IOL1 = 8.5 mA 0.7 V 2.7 V ≤ VDD < 4.0 V, IOL1 = 5.0 mA 0.7 V 1.8 V ≤ VDD < 2.
PAGE 764
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (7/8) (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, AVREF ≤ VDD, VSS = AVSS = 0 V) Parameter Supply current Note 1 Symbol Note 2 IDD1 Conditions Operating mode MIN. 1.6 2.8 mA Resonator connection 2.3 3.9 mA fXH = 10 MHz, VDD = 3.0 V, RMC = 00H Square wave input 1.5 2.7 mA Resonator connection 2.2 3.
PAGE 765
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. DC Characteristics (8/8) (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, AVREF ≤ VDD, VSS = AVSS = 0 V) Parameter Symbol Real-time counter operating current IWDT VDD = 3.0 V TYP. MAX. Unit 0.15 1 μA 0.28 0.35 μA 0.35 1.5 μA 9 18 μA AVREF = VDD = 5.0 V 1.72 3.2 mA AVREF = VDD = 3.0 V 0.72 1.6 mA Normal mode AVREF = VDD = 5.0 V 0.86 1.
PAGE 766
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. AC Characteristics (1) Basic operation (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V) Items Instruction cycle (minimum Symbol TCY instruction execution time) Conditions MIN. TYP. MAX. Unit 32 μs 0.4 Note 1 32 μs 0.4 Note 1 32 μs 125 μs 32 μs 32 μs 2.7 V ≤ VDD ≤ 5.5 V 10 MHz 1.8 V ≤ VDD < 2.
PAGE 767
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. TCY vs. VDD (Main System Clock Operation, RMC = 00H (Normal Power Mode)) 100 32 10 Cycle time TCY [ μ s] 5.0 2.0 Guaranteed operation range 1.0 0.4 0.2 0.1 0.01 0 1.0 2.0 1.8 3.0 4.0 5.0 5.5 6.0 2.7 Supply voltage VDD [V] R01UH0028EJ0400 Rev.4.
PAGE 768
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. TCY vs. VDD (Main System Clock Operation, RMC = 56H (Low Power Consumption Mode)) 100 32 10 5.0 Cycle time TCY [ μ s] Guaranteed operation range 2.0 1.0 0.4 0.2 0.1 0.01 0 1.0 2.0 3.0 4.0 5.0 5.5 6.0 1.8 Supply voltage VDD [V] AC Timing Test Points VIH VIL R01UH0028EJ0400 Rev.4.
PAGE 769
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. External Main System Clock Timing, External Subsystem Clock Timing 1/fEXCLK tEXCLKL tEXCLKH 0.8VDD (MIN.) EXCLK 0.2VDD (MAX.) 1/fEXCLKS tEXCLKSL tEXCLKSH 0.7VDD (MIN.) 0.3VDD (MAX.) EXCLKS TI Timing tTIH0 tTIL0 TI000, TI010 1/fTI5 tTIL5 tTIH5 TI50, TI51 Interrupt Request Input Timing tINTL tINTH INTP0 to INTP11 R01UH0028EJ0400 Rev.4.
PAGE 770
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Key Interrupt Input Timing tKR KR0 to KR5 RESET Input Timing tRSL RESET R01UH0028EJ0400 Rev.4.
PAGE 771
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (2) Serial interface (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V) (a) UART6 (dedicated baud rate generator output) Parameter Transfer rate R01UH0028EJ0400 Rev.4.00 Sep 27, 2010 Symbol Conditions MIN. TYP. MAX.
PAGE 772
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (b) IICA Parameter Symbol SCLA0 clock frequency Conditions Standard Mode High-Speed Mode Unit MIN. MAX. MIN. MAX. 0 100 0 400 kHz 4.7 − 0.6 − μs tHD: STA 4.0 − 0.6 − μs tLOW 4.7 − 1.3 − μs fSCL Fast mode: fPRS ≥ 3.
PAGE 773
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (c) CSI1n (master mode, SCK1n... internal clock output) Parameter SCK1n cycle time SCK1n high-/low-level width Symbol tKCY1 Conditions MIN. 2.7 V ≤ VDD ≤ 5.5 V 200 1.8 V ≤ VDD < 2.7 V 400 tKCY1/2 − 10 tKH1, TYP. MAX.
PAGE 774
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Serial Transfer Timing IICA: tLOW tR SCLA0 tHD: DAT tHIGH tF tSU: STA tHD: STA tSU: STO tSU: DAT tHD: STA SDAA0 tBUF Stop condition Start condition Restart condition Stop condition CSI1n: tKCYm tKLm tKHm SCK1n tSIKm SI1n tKSIm Input data tKSOm SO1n Remark Output data m = 1, 2 n = 0, 1 R01UH0028EJ0400 Rev.4.
PAGE 775
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Analog Characteristics (1) A/D Converter (1/2) (TA = −40 to +85°C, 1.8 V ≤ AVREF ≤ VDD ≤ 5.
PAGE 776
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (2) PGA (TA = −40 to +85°C, 2.7 V ≤ AVREF ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Input offset voltage VIOPGA Input voltage range VIPGA Maximum output voltage VOPGA Gain error Conditions MIN. TYP. ±5 SRRPGA SRFPGA ±10 mV 0.9AVREF/ gain V 0.1AVREF 0.9AVREF V 4, 8 times ±1 % 16 times ±1.
PAGE 777
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (4) Operational amplifier 1 (TA = −40 to +85°C, 2.2 V ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V, Output load: RL = 47 kΩ, CL = 50 pF) Parameter Symbol Input offset voltage VIOP1 Conditions VDD = 3.0 V Output voltage, high VOHOP1 VDD = 3.0 V/2.2 V, IOH = −500 μA Output voltage, low VOLOP1 VDD = 3.0 V/2.
PAGE 778
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (5) POC (TA = −40 to +85°C, VSS = 0 V) Parameter Symbol Detection voltage Power supply voltage rise Conditions MIN. TYP. MAX. Unit VPOR 1.52 1.61 1.70 V VPDR 1.50 1.59 1.68 V tPTH Change inclination of VDD: 0 V → VPOR 0.
PAGE 779
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (6) Supply Voltage Rise Time (TA = −40 to +85°C, VSS = 0 V) Parameter Maximum time to rise to 1.8 V (VDD (MIN.)) Symbol Note tPUP1 (VDD: 0 V → 1.8 V) Conditions MIN. LVI default start function stopped is TYP. MAX. Unit 3.6 ms 1.9 ms set (LVISTART (Option Byte) = 0), when RESET input is not used Maximum time to rise to 1.8 V (VDD (MIN.
PAGE 780
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. (7) LVI (TA = −40 to +85°C, VPDR ≤ VDD ≤ 5.5 V, VSS =0 V) Parameter Detection Symbol Supply voltage level voltage External input pin Note 1 Supply voltage when Conditions MIN. TYP. MAX. Unit VLVI0 4.12 4.22 4.32 V VLVI1 3.97 4.07 4.17 V VLVI2 3.82 3.92 4.02 V VLVI3 3.66 3.76 3.86 V VLVI4 3.51 3.61 3.71 V VLVI5 3.35 3.
PAGE 781
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C) Parameter Data retention supply voltage Symbol Conditions VDDDR MIN. 1.5 Note TYP. MAX. Unit 5.5 V Note The value depends on the POC detection voltage.
PAGE 782
78K0/Kx2-L CHAPTER 28 ELECTRICAL SPECIFICATIONS Caution The pins mounted depend on the product. Refer to Caution 2 at the beginning of this chapter. Flash Memory Programming Characteristics (TA = −40 to +85°C, 2.0 V ≤ VDD ≤ 5.5 V, VSS = 0 V) • Basic characteristics Parameter Symbol Conditions MIN.
PAGE 783
78K0/Kx2-L CHAPTER 29 PACKAGE DRAWINGS CHAPTER 29 PACKAGE DRAWINGS 29.1 78K0/KY2-L • μPD78F0550MA-FAA-AX, 78F0551MA-FAA-AX, 78F0552MA-FAA-AX, 78F0555MA-FAA-AX, 78F0556MA-FAA-AX, 78F0557MA-FAA-AX 16-PIN PLASTIC SSOP (4.4x5.0) D1 D detail of lead end 9 16 A3 E 1 c 8 L Lp ZD bp x M S HE A A2 L1 S A1 y S S e (UNIT:mm) ITEM D 5.00 ± 0.15 D1 5.20 ± 0.15 E 4.40 ± 0.20 HE 6.40 ± 0.20 A 1.725 MAX. A1 0.125 ± 0.05 A2 1.50 A3 0.25 e bp 0.65 0.22 + 0.08 0.07 c 0.15 + 0.03 0.
PAGE 784
78K0/Kx2-L CHAPTER 29 PACKAGE DRAWINGS 29.2 78K0/KA2-L • μPD78F0560MC-CAA-AX, 78F0561MC-CAA-AX, 78F0562MC-CAA-AX, 78F0565MC-CAA-AX, 78F0566MC-CAA-AX, 78F0567MC-CAA-AX 20-PIN PLASTIC SSOP (7.62 mm (300)) V 11 20 detail of lead end T I P L 10 1 U V W A W H F G J S C E D N M M K S (UNIT:mm) B ITEM A NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. B 6.50±0.10 0.325 C 0.65 (T.P.) D 0.22 +0.10 −0.05 E 0.10±0.05 F 1.
PAGE 785
78K0/Kx2-L CHAPTER 29 PACKAGE DRAWINGS • μPD78F0560FC-2N2-A, 78F0561FC-2N2-A, 78F0562FC-2N2-A, 78F0565FC-2N2-A, 78F0566FC-2N2-A, 78F0567FC-2N2-A 25-PIN PLASTIC FLGA (3x3) 21x b w S A S AB M A ZD D x e ZE 5 4 B 3 2.27 E 2 C 1 E w S B INDEX MARK y1 S D C B A D 2.27 INDEX MARK A S y S DETAIL OF C PART DETAIL OF D PART (UNIT:mm) R0.17±0.05 0.43±0.05 R0.12±0.05 0.33±0.05 0.50±0.05 0.365±0.05 b (LAND PAD) 0.34±0.05 (APERTURE OF SOLDER RESIST) 0.365±0.05 0.33±0.05 0.43±0.
PAGE 786
78K0/Kx2-L CHAPTER 29 PACKAGE DRAWINGS • μPD78F0560K8-3B4-AX, 78F0561K8-3B4-AX, 78F0562K8-3B4-AX, 78F0565K8-3B4-AX, 78F0566K8-3B4-AX, 78F0567K8-3B4-AX ± ± ± ± ± ± R01UH0028EJ0400 Rev.4.
PAGE 787
78K0/Kx2-L CHAPTER 29 PACKAGE DRAWINGS 29.3 78K0/KB2-L • μPD78F0571MC-CAB-AX, 78F0572MC-CAB-AX, 78F0573MC-CAB-AX, 78F0576MC-CAB-AX, 78F0577MC-CAB-AX, 78F0578MC-CAB-AX 30-PIN PLASTIC SSOP (7.62mm (300)) 30 V 16 detail of lead end T I P 1 U V 15 W L W A H F G J S C E D N S B M M NOTE Each lead centerline is located within 0.13 mm of its true position (T.P.) at maximum material condition. K (UNIT:mm) ITEM A B 9.70±0.10 0.30 C 0.65 (T.P.) D 0.22 +0.10 −0.05 E 0.10±0.05 F 1.
PAGE 788
78K0/Kx2-L CHAPTER 29 PACKAGE DRAWINGS 29.4 78K0/KC2-L • μPD78F0581K8-4B4-AX, 78F0582K8-4B4-AX, 78F0583K8-4B4-AX, 78F0586K8-4B4-AX, 78F0587K8-4B4-AX, 78F0588K8-4B4-AX ± ± ± ± ± + R01UH0028EJ0400 Rev.4.
PAGE 789
78K0/Kx2-L CHAPTER 29 PACKAGE DRAWINGS • μPD78F0581GB-GAF-AX, 78F0582GB-GAF-AX, 78F0583GB-GAF-AX, 78F0586GB-GAF-AX, 78F0587GB-GAF-AX, 78F0588GB-GAF-AX 44-PIN PLASTIC LQFP (10x10) HD detail of lead end D L1 33 A3 23 c 22 34 θ L Lp E HE (UNIT:mm) 44 12 11 1 ZE e ZD b x M S A S S NOTE Each lead centerline is located within 0.20 mm of its true position at maximum material condition. R01UH0028EJ0400 Rev.4.00 Sep 27, 2010 A1 DIMENSIONS 10.00±0.20 E 10.00±0.20 HD 12.00±0.
PAGE 790
78K0/Kx2-L CHAPTER 29 PACKAGE DRAWINGS • μPD78F0581GA-GAM-AX, 78F0582GA-GAM-AX, 78F0583GA-GAM-AX, 78F0586GA-GAM-AX, 78F0587GA-GAM-AX, 78F0588GA-GAM-AX 48-PIN PLASTIC LQFP (FINE PITCH) (7x7) HD D detail of lead end 36 A3 25 37 c 24 θ L Lp E L1 HE (UNIT:mm) 13 48 1 12 ZE e ZD b x M S A S A2 NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. R01UH0028EJ0400 Rev.4.00 Sep 27, 2010 A1 DIMENSIONS 7.00±0.20 E 7.00±0.20 HD 9.00±0.
PAGE 791
78K0/Kx2-L CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS CHAPTER 30 RECOMMENDED SOLDERING CONDITIONS These products should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, please contact a Renesas Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www2.renesas.com/pkg/en/mount/index.html) Table 30-1.
PAGE 792
78K0/Kx2-L CHAPTER 31 CAUTIONS FOR WAIT CHAPTER 31 CAUTIONS FOR WAIT 31.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware.
PAGE 793
78K0/Kx2-L CHAPTER 31 CAUTIONS FOR WAIT 31.2 Peripheral Hardware That Generates Wait Table 31-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks. Table 31-1.
PAGE 794
78K0/Kx2-L APPENDIX A DEVELOPMENT TOOLS APPENDIX A DEVELOPMENT TOOLS The following development tools are available for the development of systems that employ the 78K0/Kx2-L microcontrollers. Figure A-1 shows the development tool configuration. R01UH0028EJ0400 Rev.4.
PAGE 795
78K0/Kx2-L APPENDIX A DEVELOPMENT TOOLS Figure A-1.
PAGE 796
78K0/Kx2-L APPENDIX A DEVELOPMENT TOOLS Figure A-1.
PAGE 797
78K0/Kx2-L APPENDIX A DEVELOPMENT TOOLS A.1 Software Package SP78K0 Development tools (software) common to the 78K0 microcontrollers are combined in this 78K0 microcontroller software package. package A.2 Language Processing Software RA78K0 Note 1 This assembler converts programs written in mnemonics into object codes executable Assembler package with a microcontroller.
PAGE 798
78K0/Kx2-L APPENDIX A DEVELOPMENT TOOLS A.3 Flash Memory Programming Tools A.3.1 When using flash memory programmer PG-FP5 and FL-PR5 PG-FP5, FL-PR5 Flash memory programmer dedicated to microcontrollers with on-chip flash memory. Flash memory programmer FA-xxxx Note Flash memory programming adapter used connected to the flash memory programmer Flash memory programming adapter Note for use.
PAGE 799
78K0/Kx2-L APPENDIX A DEVELOPMENT TOOLS A.4 Debugging Tools (Hardware) A.4.1 When using in-circuit emulator QB-78K0KX2L In-circuit emulator This in-circuit emulator serves to debug hardware and software when developing application systems using the 78K0/Kx2-L microcontrollers. It supports to the integrated debugger (ID78K0QB). This emulator should be used in combination with a power supply unit and emulation probe, and the USB is used to connect this emulator to the host machine. A.4.
PAGE 800
78K0/Kx2-L APPENDIX B REGISTER INDEX APPENDIX B REGISTER INDEX B.1 Register Index (In Alphabetical Order with Respect to Register Names) [A] A/D converter mode register 0 (ADM0) ...................................................................................................................... 405 A/D port configuration register 0 (ADPC0) ................................................................................................. 181, 413, 437 A/D port configuration register 1 (ADPC1) ...........
PAGE 801
78K0/Kx2-L APPENDIX B REGISTER INDEX External interrupt rising edge enable register 1 (EGPCTL1) ...................................................................................... 619 [H] Hour count register (HOUR) ....................................................................................................................................... 379 [I] IICA control register 0 (IICACTL0)..................................................................................................................
PAGE 802
78K0/Kx2-L APPENDIX B REGISTER INDEX Port mode register 3 (PM3) ........................................................................................................................ 167, 324, 345 Port mode register 4 (PM4) .................................................................................................................167, 385, 400, 573 Port mode register 6 (PM6) .................................................................................................................
PAGE 803
78K0/Kx2-L APPENDIX B REGISTER INDEX 16-bit timer capture/compare register 010 (CR010) ................................................................................................... 244 16-bit timer counter 00 (TM00) ................................................................................................................................... 243 16-bit timer mode control register 00 (TMC00)...........................................................................................................
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78K0/Kx2-L APPENDIX B REGISTER INDEX B.2 Register Index (In Alphabetical Order with Respect to Register Symbol) [A] ADCR: 10-bit A/D conversion result register................................................................................................... 410 ADCRH: 8-bit A/D conversion result register H ................................................................................................. 411 ADCRL: 8-bit A/D conversion result register L.................................................
PAGE 805
78K0/Kx2-L APPENDIX B REGISTER INDEX [F] FPCTL: Self programming mode control register............................................................................................. 713 [H] HOUR: Hour count register ............................................................................................................................. 379 [I] IF0H: Interrupt request flag register 0H ........................................................................................................
PAGE 806
78K0/Kx2-L APPENDIX B REGISTER INDEX P7: Port register 7 ..................................................................................................................................... 172 P12: Port register 12 ................................................................................................................................... 172 PCC: Processor clock control register..........................................................................................................
PAGE 807
78K0/Kx2-L APPENDIX B REGISTER INDEX [T] TCL50: Timer clock selection register 50 ........................................................................................................ 318 TCL51: Timer clock selection register 51 ........................................................................................................ 318 TM00: 16-bit timer counter 00........................................................................................................................
PAGE 808
78K0/Kx2-L APPENDIX C REVISION HISTORY APPENDIX C REVISION HISTORY C.1 Major Revisions in This Edition (1/4) Page Description Classification Throughout − Addition of 78K0/KA2-L (25, 32-pin products), 78K0/KC2-L (40-pin products) − Change URL of Renesas Electronics website (d) − CHAPTER 1 OUTLINE p.4 Change of 1.2 Ordering Information (d) pp.24, 25 Change of 1.5 Outline of Functions (d) CHAPTER 2 PIN FUNCTIONS pp.27 to 30, 34, 35 Change of the state of RESET/P125 pin after reset in 2.1.
PAGE 809
78K0/Kx2-L APPENDIX C REVISION HISTORY (2/4) Page Description Classification p.212 Change of description of (9) Peripheral enable register 0 (PER0) in 5.3 Registers Controlling Clock Generator (c) p.212 Change of Figure 5-12. Format of Peripheral Enable Register 0 (PER0) (c) p.230 Addition of Note to Figure 5-18. CPU Clock Status Transition Diagram (When LVI Default Start Mode Function Stopped Is Set (Option Byte: LVISTART = 0), 78K0/KY2-L, 78K0/KA2-L, and 78K0/KB2-L) (c) p.
PAGE 810
78K0/Kx2-L APPENDIX C REVISION HISTORY (3/4) Page Description Classification CHAPTER 12 A/D CONVERTER p.421 Change of Table 12-8. Setting Functions of P70/ANI8 to P72/ANI10 Pins (d) p.433 Change of mode name in Table 12-9. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) (c) CHAPTER 13 OPERATIONAL AMPLIFIERS p.435 Change of Figure 13-1. Block Diagram of Operational Amplifier (c) p.439 Change of Figure 13-6.
PAGE 811
78K0/Kx2-L APPENDIX C REVISION HISTORY (4/4) Page Description Classification CHAPTER 25 FLASH MEMORY p.712 Change of Remark in 25.8 Flash Memory Programming by Self Programming (e) CHAPTER 26 ON-CHIP DEBUG FUNCTION p.718 Addition of Caution 2 in 26.1 Connecting QB-MINI2 to 78K0/Kx2-L Microcontrollers (c) p.720 Addition of Figure 26-1. Connection Example of QB-MINI2 and 78K0/Ix2 Microcontrollers (2/3) (c) Remark “Classification” in the above table classifies revisions as follows.
PAGE 812
78K0/Kx2-L APPENDIX C REVISION HISTORY C.2 Revision History of Preceding Editions Here is the revision history of the preceding editions. Chapter indicates the chapter of each edition. (1/8) Edition 2nd Edition Description Chapter Modification of P60 and P61 pins alternate function in the 78K0/KY2-L and 78K0/KA2-L Throughout 1.
PAGE 813
78K0/Kx2-L APPENDIX C REVISION HISTORY (2/8) Edition 2nd Edition Description Chapter Modification of Figure 4-45 Format of A/D Port Configuration Register 0 (ADPC0) CHAPTER 4 PORT Modification of Figure 4-46 Format of A/D Port Configuration Register 1 (ADPC1) (78K0/KB2-L and 78K0/KC2-L Only) FUNCTIONS Modification of PM×× and P×× value of P125 pin in Table 4-12 Settings of Port Mode Register and Output Latch When Using Alternate Function (78K0/KY2-L) to Table 415 Settings of Port Mode Register and
PAGE 814
78K0/Kx2-L APPENDIX C REVISION HISTORY (3/8) Edition 2nd Edition Description Modification of Table 12-3 Setting Functions of P10/ANI8/AMP1-, P12/ANI10/AMP1+ Pins Chapter CHAPTER 12 A/D CONVERTER Modification of Table 12-5 Setting Functions of P20/ANI0/AMP0-, P22/ANI2/AMP0+ Pins Deletion of Caution 2 in 12.4.1 Basic operations of A/D converter Modification of description of setting methods and deletion of Caution 2 in 12.4.
PAGE 815
78K0/Kx2-L APPENDIX C REVISION HISTORY (4/8) Edition Description Chapter 2nd Edition Modification of Caution in Figure 17-14 Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) (78K0/KB2-L) to Figure 17-16 Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) (48-pin products of 78K0/KC2-L) CHAPTER 17 Addition of Caution 4 to 19.1.
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78K0/Kx2-L APPENDIX C REVISION HISTORY (5/8) Edition Description 2nd Edition Modification of Caution in Figure 17-14 Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) (78K0/KB2-L) to Figure 17-16 Format of Priority Specification Flag Registers (PR0L, PR0H, PR1L, PR1H) (48-pin products of 78K0/KC2-L) Chapter CHAPTER 28 ELECTRICAL SPECIFICATIONS (TARGET VALUES) • Addition of reset current (IDDrst) (1) A/D Converter in Analog Characteristics • Modification of conversion time (tCON
PAGE 817
78K0/Kx2-L APPENDIX C REVISION HISTORY (6/8) Edition 3rd Edition Description Chapter Modification of Related Documents INTRODUCTION Modification of description in 1.1 Features CHAPTER 1 Modification of Caution 1 in 1.3.3 78K0/KB2-L and 1.3.4 78K0/KC2-L OUTLINE Modification of Caution 1 in 1.4.3 78K0/KB2-L and 1.4.4 78K0/KC2-L Modification of description in 1.
PAGE 818
78K0/Kx2-L APPENDIX C REVISION HISTORY (7/8) Edition 3rd Edition Description Chapter Modification of Table 12-6 Setting Functions of P21/ANI1/AMP0OUT/PGAIN Pin CHAPTER 12 A/D Modification of <4> in 12.4.
PAGE 819
78K0/Kx2-L APPENDIX C REVISION HISTORY (8/8) Edition 3rd Edition Description Chapter Modification of Figure 21-2 Timing of Generation of Internal Reset Signal by Poweron-Clear Circuit and Low-Voltage Detector CHAPTER 21 Modification of 23.1 Regulator Overview CHAPTER 23 Addition of 23.
PAGE 820
78K0/Kx2-L User’s Manual: Hardware Publication Date: Rev.0.01 Rev.4.
PAGE 821
http://www.renesas.com SALES OFFICES Refer to "http://www.renesas.com/" for the latest and detailed information. Renesas Electronics America Inc. 2880 Scott Boulevard Santa Clara, CA 95050-2554, U.S.A. Tel: +1-408-588-6000, Fax: +1-408-588-6130 Renesas Electronics Canada Limited 1101 Nicholson Road, Newmarket, Ontario L3Y 9C3, Canada Tel: +1-905-898-5441, Fax: +1-905-898-3220 Renesas Electronics Europe Limited Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, U.
PAGE 822
78K0/Kx2-L R01UH0028EJ0400 (Previous Number: U19111EJ3V0UD00)