Datasheet

CHAPTER 4 PORT FUNCTIONS
User’s Manual U18698EJ1V0UD
97
(2) Port registers (P1 to P4, P10 to P12, P14, P15)
These registers write the data that is output from the chip when data is output from a port.
If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is
read.
These registers can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 4-17 Format of Port Register
7Symbol
P1
6543
P13
2
P12
1 0 Address
FF01H
After reset
00H (output latch)
R/W
R/W
R/W
P2
P25 P24 P23 P22 P21 P20
FF02H 00H (output latch)
0
P3
0 0 P34 P33 P32 P31
FF03H 00H (output latch) R/W
P4
P40
FF04H 00H (output latch) R/W
0
P10
000
0 0 P143 P142
P101 P100
FF0AH 00H (output latch) R/W
0
P12
0 0 P120 FF0CH 00H (output latch) R/W
0
P14
0 P141 P140
FF0EH 00H (output latch) R/W
0
P11
0 0 0 P113 P112
FF0BH 00H (output latch) R/W
0 0 P153 P152
0
P15
0 P151 P150
FF0FH 00H (output latch) R/W
0000 00
00
0
0000000
00
00
P124 P123 P122 P121
Note 2
Note 2 Note 2
Note 2
Note 1
Note 1
m = 1 to 4, 10 to 12, 14, 15; n = 0 to 5
Pmn
Output data control (in output mode) Input data read (in input mode)
0 Output 0 Input low level
1 Output 1 Input high level
Notes 1. P121 to P124 are read-only. These become undefined at reset.
2. When the operation mode of the pin is the clock input mode, 0 is always read.