Datasheet

CHAPTER 3 CPU ARCHITECTURE
User’s Manual U18698EJ1V0UD
62
Table 3-6. Special Function Register List (3/4)
Manipulatable Bit Unit Address Special Function Register (SFR) Name Symbol R/W
1 Bit 8 Bits 16 Bits
After
Reset
FF66H Day count register DAY R/W
− √ −
01H
FF67H Month count register MONTH R/W
− √ −
01H
FF68H Year count register YEAR R/W
− √ −
00H
FF69H 8-bit timer H mode register 0 TMHMD0 R/W
√ √ −
00H
FF6AH Timer clock selection register 50 TCL50 R/W
√ √ −
00H
FF6BH 8-bit timer mode control register 50 TMC50 R/W
√ √ −
00H
FF6CH 8-bit timer H mode register 1 TMHMD1 R/W
√ √ −
00H
FF6DH 8-bit timer H carrier control register 1 TMCYC1 R/W
√ √ −
00H
FF6EH Key return mode register KRM R/W
√ √ −
00H
FF6FH
8-bit timer counter 51 TM51 R
− √ −
00H
FF70H
Asynchronous serial interface operation mode
register 0
ASIM0 R/W
√ √ −
01H
FF71H Baud rate generator control register 0 BRGC0 R/W
− √ −
1FH
FF72H Receive buffer register 0 RXB0 R
− √ −
FFH
FF73H
Asynchronous serial interface reception error
status register 0
ASIS0 R
− √ −
00H
FF74H Transmit shift register 0 TXS0 W
− √ −
FFH
FF82H Clock error correction register SUBCUD R/W
√ √ −
00H
FF86H Alarm minute register ALARMWM R/W
− √ −
00H
FF87H Alarm hour register ALARMWH R/W
− √ −
12H
FF88H Alarm week register ALARMWW R/W
− √ −
00H
FF89H Real-time counter control register 0 RTCC0 R/W
√ √ −
00H
FF8AH Real-time counter control register 1 RTCC1 R/W
√ √ −
00H
FF8BH Real-time counter control register 2 RTCC2 R/W
√ √ −
00H
FF8CH Timer clock selection register 51 TCL51 R/W
√ √ −
00H
FF8DH A/D converter mode register
Note 1
ADM R/W
√ √ −
00H
FF8EH Analog input channel specification register
Note 1
ADS R/W
√ √ −
00H
FF8FH A/D port configuration register 0
Note 1
ADPC0 R/W
√ √ −
08H
FF99H Watchdog timer enable register WDTE R/W
− √ −
Note 2
1AH/9AH
FF9FH Clock operation mode select register OSCCTL R/W
√ √ −
00H
FFA0H Internal oscillation mode register RCM R/W
√ √ −
80H
Note 3
FFA1H Main clock mode register MCM R/W
√ √ −
00H
FFA2H Main OSC control register MOC R/W
√ √ −
80H
FFA3H Oscillation stabilization time counter status
register
OSTC R
√ √ −
00H
FFA4H Oscillation stabilization time select register OSTS R/W
− √ −
05H
FFACH Reset control flag register RESF R
− √ −
00H
Note 4
Notes 1.
μ PD78F041x only.
2. The reset value of WDTE is determined by the setting of the option byte.
3. The value of this register is 00H immediately after a reset release but automatically changes to 80H after
oscillation accuracy stabilization of high-speed internal oscillator has been waited.
4. The reset value of RESF varies depending on the reset source.