Datasheet

CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)
User’s Manual U18698EJ1V0UD
550
Standard
p
roducts
AC Characteristics
(1) Basic operation
(T
A = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V)
Parameter Symbol Conditions MIN. TYP. MAX. Unit
2.7 V ≤ VDD ≤ 5.5 V 0.2 16 μ s
Main system clock (fXP)
operation
1.8 V ≤ V
DD < 2.7 V 0.4 16 μ s
Instruction cycle (minimum
instruction execution time)
T
CY
Subsystem clock (f
SUB) operation 114 122 125 μ s
2.7 V ≤ VDD ≤ 5.5 V 10 MHz XSEL = 1
1.8 V ≤ V
DD < 2.7 V 5 MHz
2.7 V ≤ VDD ≤ 5.5 V 7.6 8.4 MHz
Peripheral hardware clock
frequency
f
PRS
XSEL = 0
1.8 V ≤ V
DD < 2.7 V
Note 1
6.75 8.4 MHz
2.7 V ≤ VDD ≤ 5.5 V 2.0 10.0 MHz
External main system clock
frequency
f
EXCLK
1.8 V ≤ V
DD < 2.7 V 2.0 5.0 MHz
2.7 V ≤ VDD ≤ 5.5 V 48 500 ns
External main system clock
input high-level width, low-level
width
tEXCLKH,
t
EXCLKL
1.8 V ≤ V
DD < 2.7 V 96 500 ns
2.7 V ≤ VDD ≤ 5.5 V
2/f
sam +
0.2
Note 2
μ s
TI000 input high-level width,
low-level width
tTIH0,
t
TIL0
1.8 V ≤ V
DD < 2.7 V
2/f
sam +
0.5
Note 2
μ s
4.0 V ≤ VDD ≤ 5.5 V 16 MHz
2.7 V ≤ VDD < 4.0 V 10 MHz
TI52 input frequency fTI5
1.8 V ≤ V
DD < 2.7 V 5 MHz
4.0 V ≤ VDD ≤ 5.5 V 31.25 ns
2.7 V ≤ VDD < 4.0 V 50 ns
TI52 input high-level width, low-
level width
tTIH5,
t
TIL5
1.8 V ≤ V
DD < 2.7 V 100 ns
Interrupt input high-level width,
low-level width
tINTH,
t
INTL
1
μ s
Key return input low-level width tKR 250 ns
RESET low-level width tRSL 10 μ s
Notes 1. A characteristic of the main system clock frequency. Set the clock divider to be set using a peripheral
function to fRH/2 or less.
2. Selection of f
sam = fPRS, fPRS/4, fPRS/256 is possible using bits 0 and 1 (PRM000, PRM001) of prescaler
mode registers 00 (PRM00). Note that when selecting the TI000 valid edge as the count clock, f
sam = fPRS.