Datasheet

CHAPTER 22 LOW-VOLTAGE DETECTOR
User’s Manual U18698EJ1V0UD
496
Figure 22-7. Timing of Low-Voltage Detector Interrupt Signal Generation
(Detects Level of Supply Voltage (V
DD)) (1/2)
(1) In 1.59 V POC mode (option byte: POCMODE = 0)
Supply voltage (V DD )
Time
<1>
Note 1
<8> Cleared by software
LVIMK flag
(set by software)
LVIF flag
INTLVI
LVIIF flag
Internal reset signal
<4>
<6>
<7>
Cleared by software
<5> Wait time
LVION flag
(set by software)
Note 2
Note 2
<3>
L
LVISEL flag
(set by software)
<2>
LVIMD flag
(set by software)
L
<9>
V LVI
V POC = 1.59 V (TYP.)
Note 2
Note 3
Note 3
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. The interrupt request signal (INTLVI) is generated and the LVIF and LVIIF flags may be set (1).
3. If LVION is cleared (0) in a state below the LVI detection voltage, an INTLVI signal is generated and
LVIIF becomes 1.
Remark <1> to <9> in Figure 22-7 above correspond to <1> to <9> in the description of “When starting
operation” in 22.4.2 (1) When detecting level of supply voltage (V
DD).