Datasheet

CHAPTER 22 LOW-VOLTAGE DETECTOR
User’s Manual U18698EJ1V0UD
494
Figure 22-6. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Detects Level of Input Voltage from External Input Pin (EXLVI))
Input voltage from
external input pin (EXLVI)
LVI detection voltage
(V
EXLVI)
<1>
Time
LVIMK flag
(set by software)
LVIF flag
LVIRF flag
Note 3
Note 2
LVI reset signal
Internal reset signal
Cleared by
software
Not cleared Not cleared
Not cleared Not cleared
Cleared by
software
<3>
<6>
LVION flag
(set by software)
LVIMD flag
(set by software)
H
Note 1
LVISEL flag
(set by software)
<5>
<2>
Not clearedNot cleared
<4> Wait time
Not cleared
Not cleared
Not cleared
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. The LVIF flag may be set (1).
3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 20
RESET FUNCTION.
Remark <1> to <6> in Figure 22-6 above correspond to <1> to <6> in the description of “When starting
operation” in 22.4.1 (2) When detecting level of input voltage from external input pin (EXLVI).