Datasheet

CHAPTER 22 LOW-VOLTAGE DETECTOR
User’s Manual U18698EJ1V0UD
492
Figure 22-5. Timing of Low-Voltage Detector Internal Reset Signal Generation
(Detects Level of Supply Voltage (V
DD)) (2/2)
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
S
upply voltage (V DD )
V
LVI
<3>
<1>
Tim
e
LVIMK flag
(set by software)
LVIF flag
LVIRF flag
Note 3
Note 2
LVI reset signal
POC reset signal
Internal reset signal
Cleared by
software
Not cleared Not cleared
Not cleared Not cleared
Cleared by
software
<4>
<7>
Clear
Clear
Clear
<5> Wait time
LVION flag
(set by software)
LVIMD flag
(set by software)
H
Note 1
L
LVISEL flag
(set by software)
<6>
<2>
2.7 V (TYP.)
V
POC = 1.59 V (TYP.)
Notes 1. The LVIMK flag is set to “1” by reset signal generation.
2. The LVIF flag may be set (1).
3. LVIRF is bit 0 of the reset control flag register (RESF). For details of RESF, see CHAPTER 20
RESET FUNCTION.
Remark <1> to <7> in Figure 22-5 above correspond to <1> to <7> in the description of “When starting
operation” in 22.4.1 (1) When detecting level of supply voltage (V
DD).