Datasheet

CHAPTER 21 POWER-ON-CLEAR CIRCUIT
User’s Manual U18698EJ1V0UD
482
Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit
and Low-Voltage Detector (2/2)
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
Internal high-speed
oscillation clock (f
RH )
High-speed
system clock (f
XH )
(when X1 oscillation
is selected)
Starting oscillation is
specified by software.
Internal reset signal
Operation
stops
Normal operation
(internal high-speed
oscillation clock)
Note 2
Normal operation
(internal high-speed
oscillation clock)
Note 2
Operation stops
Reset period
(oscillation
stop)
Reset period
(oscillation
stop)
Normal operation
(internal high-speed
oscillation clock)
Note 2
Starting oscillation is
specified by software.
Starting oscillation is
specified by software.
CPU
0 V
Supply voltage
(V
DD)
1.8 V
Note 1
Reset processing (11 to 47 s)
μ
Reset processing (11 to 47 s)
μ
Reset processing (11 to 47 s)
μ
Set LVI to be
used for reset
Set LVI to be
used for reset
Set LVI to be
used for interrupt
Wait for oscillation
accuracy stabilization
(86 to 361 s)
μ
Wait for oscillation
accuracy stabilization
(86 to 361 s)
μ
Wait for oscillation
accuracy stabilization
(86 to 361 s)
μ
VDDPOC = 2.7 V (TYP.)
V
POC = 1.59 V (TYP.)
V LVI
Notes 1. The operation guaranteed range is 1.8 V ≤ V
DD ≤ 5.5 V. To make the state at lower than 1.8 V reset
state when the supply voltage falls, use the reset function of the low-voltage detector, or input the low
level to the RESET pin.
2. The internal high-speed oscillation clock and a high-speed system clock or subsystem clock can be
selected as the CPU clock. To use the X1 clock, use the OSTC register to confirm the lapse of the
oscillation stabilization time. To use the XT1 clock, use the timer function for confirmation of the lapse
of the stabilization time.
Cautions 1. Set the low-voltage detector by software after the reset status is released (see CHAPTER 22
LOW-VOLTAGE DETECTOR).
2. A voltage oscillation stabilization time of 1.93 to 5.39 ms is required after the supply voltage
reaches 1.59 V (TYP.). If the supply voltage rises from 1.59 V (TYP.) to 2.7 V (TYP.) within 1.93
ms, the power supply oscillation stabilization time of 0 to 5.39 ms is automatically generated
before reset processing.
Remark V
LVI: LVI detection voltage
V
POC: POC detection voltage