Datasheet

CHAPTER 21 POWER-ON-CLEAR CIRCUIT
User’s Manual U18698EJ1V0UD
480
21.2 Configuration of Power-on-Clear Circuit
The block diagram of the power-on-clear circuit is shown in Figure 21-1.
Figure 21-1. Block Diagram of Power-on-Clear Circuit
−
+
Reference
voltage
source
Internal reset signal
V DD
V DD
21.3 Operation of Power-on-Clear Circuit
(1) In 1.59 V POC mode (option byte: POCMODE = 0)
• An internal reset signal is generated on power application. When the supply voltage (V
DD) exceeds the
detection voltage (VPOC = 1.59 V ±0.15 V), the reset status is released.
• The supply voltage (V
DD) and detection voltage (VPOC = 1.59 V ±0.15 V) are compared. When VDD < VPOC, the
internal reset signal is generated. It is released when V
DD ≥ VPOC.
(2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1)
• An internal reset signal is generated on power application. When the supply voltage (V
DD) exceeds the
detection voltage (VDDPOC = 2.7 V ±0.2 V), the reset status is released.
• The supply voltage (V
DD) and detection voltage (VPOC = 1.59 V ±0.15 V) are compared. When VDD < VPOC, the
internal reset signal is generated. It is released when V
DD ≥ VDDPOC.
The timing of generation of the internal reset signal by the power-on-clear circuit and low-voltage detector is
shown below.