Datasheet

CHAPTER 20 RESET FUNCTION
User’s Manual U18698EJ1V0UD
476
Table 20-2. Hardware Statuses After Reset Acknowledgment (2/3)
Hardware Status After Reset
Acknowledgment
Note 1
Compare registers 00, 10, 01, 11, 02, 12 (CMP00, CMP10, CMP01, CMP11,
CMP02, CMP12)
00H
Mode registers (TMHMD0, TMHMD1, TMHMD2) 00H
8-bit timers H0, H1, H2
Carrier control register 1 (TMCYC1)
Note 2
00H
Clock selection register (RTCCL) 00H
Sub-count register (RSUBC) 0000H
Second count register (SEC) 00H
Minute count register (MIN) 00H
Hour count register (HOUR) 12H
Week count register (WEEK) 00H
Day count register (DAY) 01H
Month count register (MONTH) 01H
Year count register (YEAR) 00H
Watch error correction register (SUBCUD) 00H
Alarm minute register (ALARMWM) 00H
Alarm hour register (ALARMWH) 12H
Alarm week register (ALARMWW) 00H
Control register 0 (RTCC0) 00H
Control register 1 (RTCC1) 00H
Real-time counter
Control register 2 (RTCC2) 00H
buzzer output controller Clock output selection register (CKS) 00H
Watchdog timer
Enable register (WDTE) 1AH/9AH
Note 3
10-bit A/D conversion result register (ADCR) 0000H
8-bit A/D conversion result register (ADCRH) 00H
A/D converter mode register (ADM) 00H
Analog input channel specification register (ADS) 00H
10-bit successive
approximation type
A/D converter
Note 4
A/D port configuration register 0 (ADPC0) 08H
Receive buffer register 0 (RXB0) FFH
Transmit shift register 0 (TXS0) FFH
Asynchronous serial interface operation mode register 0 (ASIM0) 01H
Asynchronous serial interface reception error status register 0 (ASIS0) 00H
Serial interface UART0
Baud rate generator control register 0 (BRGC0) 1FH
Notes 1. During reset signal generation or oscillation stabilization time wait, only the PC contents among the
hardware statuses become undefined. All other hardware statuses remain unchanged after reset.
2. 8-bit timer H1 only.
3. The reset value of WDTE is determined by the option byte setting.
4.
μ PD78F041x only.