Datasheet

CHAPTER 20 RESET FUNCTION
User’s Manual U18698EJ1V0UD
474
Table 20-1. Operation Statuses During Reset Period
Item During Reset Period
System clock Clock supply to the CPU is stopped.
fRH Operation stopped
fX Operation stopped (pin is I/O port mode)
Main system clock
fEXCLK Clock input invalid (pin is I/O port mode)
Subsystem clock fXT Operation stopped (pin is I/O port mode)
fRL
CPU
Flash memory
RAM
Port (latch)
16-bit timer/event
counter
00
50
51
8-bit timer/event
counter
52
H0
H1
8-bit timer
H2
Real-time counter
Watchdog timer
Buzzer output
10-bit successive approximation
type A/D converter
Note
UART0 Serial interface
UART6
LCD controller/driver
Manchester code generator
Operation stopped
Power-on-clear function Operable
Low-voltage detection function
External interrupt
Operation stopped
Note
μ PD78F041x only.
Remark f
RH: Internal high-speed oscillation clock
f
X: X1 oscillation clock
f
EXCLK: External main system clock
f
XT: XT1 oscillation clock
f
RL: Internal low-speed oscillation clock