Datasheet

CHAPTER 20 RESET FUNCTION
User’s Manual U18698EJ1V0UD
472
Figure 20-2. Timing of Reset by RESET Input
Delay Delay
(5 s (TYP.))
Hi-Z
Normal operationCPU clock
Reset period
(oscillation stop)
Normal operation
(internal high-speed oscillation clock)
RESET
Internal reset signal
Port pin
High-speed system clock
(when X1 oscillation is selected)
Internal high-speed
oscillation clock
Starting X1 oscillation is specified by software.
Reset
processing
(11 to 47 s)
μ
μ
Wait for oscillation
accuracy stabilization
(86 to 361 s)
μ
Figure 20-3. Timing of Reset Due to Watchdog Timer Overflow
Normal operation
Reset period
(oscillation stop)
CPU clock
Watchdog timer
overflow
Internal reset signal
Hi-Z
Port pin
High-speed system clock
(when X1 oscillation is selected)
Internal high-speed
oscillation clock
Starting X1 oscillation is specified by software.
Normal operation
(internal high-speed oscillation clock)
Reset
processing
(11 to 47 s)
μ
Wait for oscillation
accuracy stabilization
(86 to 361 s)
μ
Caution A watchdog timer internal reset resets the watchdog timer.