Datasheet

CHAPTER 3 CPU ARCHITECTURE
User’s Manual U18698EJ1V0UD
45
Figure 3-4. Memory Map ( μ PD78F0403, 78F0413)
Special function registers
(SFR)
256 x 8 bits
Internal high-speed RAM
1024 x 8 bits
General-purpose
registers
32 x 8 bits
Reserved
Flash memory
32768 x 8 bits
Program
memory space
Data memory
space
FFFFH
FF00H
FEFFH
FEE0H
FEDFH
FB00H
FAFFH
8000H
7FFFH
0000H
0800H
07FFH
1000H
0FFFH
0040H
003FH
0000H
0085H
0084H
Program area
1905 × 8 bits
Program area
7FFFH
Program area
0080H
007FH
1080H
107FH
008FH
008EH
1085H
1084H
108FH
108EH
Vector table area
64 × 8 bits
CALLT table area
64 × 8 bits
Option byte area
Note 1
5 × 8 bits
On-chip debug security
ID setting area
Note 1
10 × 8 bits
Option byte area
Note 1
5 × 8 bits
CALLF entry area
2048 × 8 bits
1FFFH
Boot cluster 0
Note 2
Boot cluster 1
On-chip debug security
ID setting area
Note 1
10 × 8 bits
FA56H
FA55H
LCD display RAM
22 × 8 bits
FA40H
FA3FH
Reserved
Notes 1. When boot swap is not used: Set the option bytes to 0080H to 0084H, and the on-chip debug security
IDs to 0085H to 008EH.
When boot swap is used: Set the option bytes to 0080H to 0084H and 1080H to 1084H, and the
on-chip debug security IDs to 0085H to 008EH and 1085H to 108EH.
2. Writing boot cluster 0 can be prohibited depending on the setting of security (see 24.7 Security
Setting).
Remark The flash memory is divided into blocks (one block = 1 KB). For the address values and block numbers,
see Table 3-2 Correspondence Between Address Values and Block Numbers in Flash Memory.
Block 00H
Block 01H
Block 1FH
1 KB
7FFFH
07FFH
0000H
0400H
03FFH
7C00H
7BFFH