Datasheet

CHAPTER 19 STANDBY FUNCTION
User’s Manual U18698EJ1V0UD
461
Table 19-1. Operating Statuses in HALT Mode (2/2)
When HALT Instruction Is Executed While CPU Is Operating on Subsystem Clock HALT Mode Setting
Item
When CPU Is Operating on XT1 Clock (fXT)
System clock Clock supply to the CPU is stopped
fRH
fX
Status before HALT mode was set is retained
Main system clock
fEXCLK Operates or stops by external clock input
Subsystem clock fXT Operation continues (cannot be stopped)
fRL Status before HALT mode was set is retained
CPU
Flash memory
Operation stopped
RAM
Port (latch)
Status before HALT mode was set is retained
16-bit timer/event counter 00
Note 1
50
51
8-bit timer/event
counter
52
Note 1
H0
H1
8-bit timer
H2
Real-time counter
Operable
Watchdog timer Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Buzzer output
10-bit successive approximation
type A/D converter
Note 2
Operable. However, operation disabled when peripheral hardware clock (fPRS) is stopped.
UART0 Serial interface
UART6
LCD controller/driver
Manchester code generator
Power-on-clear function
Low-voltage detection function
External interrupt
Operable
Notes 1. When the CPU is operating on the subsystem clock and the internal high-speed oscillation clock has been
stopped, do not start operation of these functions on the external clock input from peripheral hardware pins.
2.
μ PD78F041x only.
Remark f
RH: Internal high-speed oscillation clock
f
X: X1 clock
f
EXCLK: External main system clock
f
XT: XT1 clock
f
RL: Internal low-speed oscillation clock