Datasheet

CHAPTER 19 STANDBY FUNCTION
User’s Manual U18698EJ1V0UD
460
Table 19-1. Operating Statuses in HALT Mode (1/2)
When HALT Instruction Is Executed While CPU Is Operating on Main System Clock HALT Mode Setting
Item
When CPU Is Operating on
Internal High-Speed
Oscillation Clock (fRH)
When CPU Is Operating on
X1 Clock (f
X)
When CPU Is Operating on
External Main System Clock
(f
EXCLK)
System clock Clock supply to the CPU is stopped
fRH Operation continues (cannot
be stopped)
Status before HALT mode was set is retained
fX Status before HALT mode
was set is retained
Operation continues (cannot
be stopped)
Status before HALT mode
was set is retained
Main system clock
fEXCLK Operates or stops by external clock input Operation continues (cannot
be stopped)
Subsystem clock fXT Status before HALT mode was set is retained
fRL Status before HALT mode was set is retained
CPU
Flash memory
Operation stopped
RAM
Port (latch)
Status before HALT mode was set is retained
16-bit timer/event counter 00
50
51
8-bit timer/event
counter
52
H0
H1
8-bit timer
H2
Real-time counter
Operable
Watchdog timer Operable. Clock supply to watchdog timer stops when “internal low-speed oscillator can be
stopped by software” is set by option byte.
Buzzer output
10-bit successive approximation
type A/D converter
Note
UART0 Serial interface
UART6
LCD controller/driver
Manchester code generator
Remote controller receiver
Power-on-clear function
Low-voltage detection function
External interrupt
Operable
Note
μ PD78F041x only.
Remark fRH: Internal high-speed oscillation clock
f
X: X1 clock
f
EXCLK: External main system clock
f
XT: XT1 clock
f
RL: Internal low-speed oscillation clock