Datasheet

CHAPTER 17 INTERRUPT FUNCTIONS
User’s Manual U18698EJ1V0UD
445
(4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN)
These registers specify the valid edge for INTP0 to INTP3.
EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears these registers to 00H.
Figure 17-5. Format of External Interrupt Rising Edge Enable Register (EGP)
and External Interrupt Falling Edge Enable Register (EGN)
Address: FF48H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGP 0 0 0 0 EGP3 EGP2 EGP1 EGP0
Address: FF49H After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
EGN 0 0 0 0 EGN3 EGN2 EGN1 EGN0
EGPn EGNn INTPn pin valid edge selection (n = 0 to 3)
0 0 Edge detection disabled
0 1 Falling edge
1 0 Rising edge
1 1 Both rising and falling edges
Table 17-3 shows the ports corresponding to EGPn and EGNn.
Table 17-3. Ports Corresponding to EGPn and EGNn
Detection Enable Register Edge Detection Port Interrupt Request Signal
EGP0 EGN0 P120/EXLVI INTP0
EGP1 EGN1 P34/TI52/TI010/TO00/RTC1HZ INTP1
EGP2 EGN2 P33/TI000/RTCDIV/RTCCL/BUZ INTP2
EGP3 EGN3 P31/TOH1 INTP3
Caution Select the port mode by clearing EGPn and EGNn to 0 because an edge may be
detected when the external interrupt function is switched to the port function.
Remark n = 0 to 3