Datasheet

CHAPTER 17 INTERRUPT FUNCTIONS

User’s Manual U18698EJ1V0UD

441

(1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H)

The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is

executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or

upon reset signal generation.

When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt

routine is entered.

IF0L, IF0H, IF1L, and IF1H are set by a 1-bit or 8-bit memory manipulation instruction. When IF0L and IF0H, and

IF1L and IF1H are combined to form 16-bit registers IF0 and IF1, they are set by a 16-bit memory manipulation

instruction.

Reset signal generation clears these registers to 00H.

Figure 17-2. Format of Interrupt Request Flag Registers (IF0L, IF0H, IF1L, IF1H)

Address: FFE0H After reset: 00H R/W

Symbol <7> 6 5 <4> <3> <2> <1> <0>

IF0L SREIF6 0 0 PIF3 PIF2 PIF1 PIF0 LVIIF

Address: FFE1H After reset: 00H R/W

Symbol <7> <6> <5> <4> <3> <2> <1> <0>

IF0H TMIF010 TMIF000 TMIF50 TMIFH0 TMIFH1 STIF0 STIF6 SRIF6

Address: FFE2H After reset: 00H R/W

Symbol <7> 6 <5> <4> <3> <2> <1> <0>

IF1L TMIF52 0 RTCIF KRIF TMIF51 RTCIIF SRIF0 ADIF

Note

Address: FFE3H After reset: 00H R/W

Symbol 7 6 5 4 3 2 <1> <0>

IF1H 0 0 0 0 0 0 MCGIF TMHIF2

XXIFX Interrupt request flag

0 No interrupt request signal is generated

1 Interrupt request is generated, interrupt request status

Note

PD78F041x only.

Cautions 1. Be sure to clear bits 5 and 6 of IF0L, and bit 6 of IF1L, and bits 2 to 7 of IF1H to 0.

2. When operating a timer, serial interface, or A/D converter after standby release, operate it

once after clearing the interrupt request flag. An interrupt request flag may be set by noise.