Datasheet

CHAPTER 17 INTERRUPT FUNCTIONS
User’s Manual U18698EJ1V0UD
436
Table 17-1. Interrupt Source List (1/2)
Interrupt Source
Interrupt
Type
Default
Priority
Note 1
Name Trigger
Internal/
External
Vector
Table
Address
Basic
Configuration
Type
Note 2
0 INTLVI Low-voltage detection
Note 3
Internal 0004H (A)
1 INTP0 0006H
2 INTP1 0008H
3 INTP2 000AH
4 INTP3
Pin input edge detection External
000CH
(B)
5 INTSRE6 UART6 reception error generation 0012H
6 INTSR6 End of UART6 reception 0014H
7 INTST6 End of UART6 transmission 0016H
8 INTST0 End of UART0 transmission 0018H
9 INTTMH1
Match between TMH1 and CMP01
(when compare register is specified)
001AH
10 INTTMH0
Match between TMH0 and CMP00
(when compare register is specified)
001CH
11 INTTM50
Match between TM50 and CR50
(when compare register is specified)
001EH
12 INTTM000
Match between TM00 and CR000
(when compare register is specified),
TI010 pin valid edge detection
(when capture register is specified)
0020H
13 INTTM010
Match between TM00 and CR010
(when compare register is specified),
TI000 pin valid edge detection
(when capture register is specified)
0022H
14 INTAD
Note 5
End of 10-bit successive approximation type
A/D conversion
0024H
15 INTSR0
End of UART0 reception or reception error
generation
0026H
16 INTRTC
Fixed-cycle signal of real-time counter/alarm
match detection
0028H
17
INTTM51
Note 4
Match between TM51 and CR51
(when compare register is specified)
Internal
002AH
(A)
18 INTKR Key interrupt detection External 002CH (C)
Maskable
19 INTRTCI Interval signal detection of real-time counter Internal 002EH (A)
Notes 1. The default priority determines the sequence of processing vectored interrupts if two or more maskable
interrupts occur simultaneously. Zero indicates the highest priority and 22 indicates the lowest priority.
2. Basic configuration types (A) to (D) correspond to (A) to (D) in Figure 17-1.
3. When bit 1 (LVIMD) of the low-voltage detection register (LVIM) is cleared to 0.
4. When 8-bit timer/event counter 51 and 8-bit timer H1 are used in the carrier generator mode, an
interrupt is generated upon the timing when the INTTM5H1 signal is generated (see Figure 8-15
Transfer Timing).
5.
μ PD78F041x only.