Datasheet

CHAPTER 16 MANCHESTER CODE GENERATOR
User’s Manual U18698EJ1V0UD
418
(b) MCG control register 1 (MC0CTL1)
This register is used to set the base clock of the Manchester code generator.
This register can be set by an 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.
Address: FF4DH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
MC0CTL1 0 0 0 0 0 MC0CKS2 MC0CKS1 MC0CKS0
MC0CKS2 MC0CKS1 MC0CKS0 Base clock (fXCLK) selection
Note 1
0 0 0 fPRS
Note 2
(10 MHz)
0 0 1 fPRS/2 (5 MHz)
0 1 0 fPRS/2
2
(2.5 MHz)
0 1 1 fPRS/2
3
(1.25 MHz)
1 0 0 fPRS/2
4
(625 kHz)
1 0 1 fPRS/2
5
(312.5 kHz)
1 1 0
1 1 1
Setting prohibited
Notes 1. If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL =
1), the fPRS operating frequency varies depending on the supply voltage.
• V
DD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• VDD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
2. If the peripheral hardware clock (f
PRS) operates on the internal high-speed oscillation clock
(fRH) (XSEL = 0), when 1.8 V ≤ VDD < 2.7 V, the setting of MC0CKS2 = MC0CKS1 =
MC0CKS0 = 0 (base clock: fPRS) is prohibited.
Caution Clear bit 7 (MC0PWR) of the MC0CTL0 register to 0 before rewriting the MC0CKS2 to
MC0CKS0 bits.
Remarks 1. f
PRS: Peripheral hardware clock frequency
2. Figures in parentheses are for operation with fPRS = 10 MHz.