Datasheet

CHAPTER 15 LCD CONTROLLER/DRIVER
User’s Manual U18698EJ1V0UD 383
(3) LCD clock control register (LCDC0)
LCDC0 specifies the LCD source clock and LCD clock.
The frame frequency is determined according to the LCD clock and the number of time slices.
LCDC0 is set using a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets LCDC0 to 00H.
Figure 15-4. Format of LCD Clock Control Register
Address: FFB2H
After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
LCDC0 0 LCDC6 LCDC5 LCDC4 0 LCDC2 LCDC1 LCDC0
LCDC6 LCDC5 LCDC4 LCD source clock (fLCD) selection
0 0 0 fXT (32.768 kHz)
0 0 1 fPRS/2
6
0 1 0 fPRS/2
7
0 1 1 fPRS/2
8
1 0 0 fRL/2
3
Other than above Setting prohibited
LCDC2 LCDC1 LCDC0 LCD clock (LCDCL) selection
0 0 0 fLCD/2
4
0 0 1 fLCD/2
5
0 1 0 fLCD/2
6
0 1 1 fLCD/2
7
1 0 0 fLCD/2
8
1 0 1 fLCD/2
9
Other than above Setting prohibited
Caution Bits 3 and 7 must be set to 0.
Remarks 1. f
XT: XT1 clock oscillation frequency
2. f
PRS: Peripheral hardware clock frequency
3. f
RL: Internal low-speed oscillation clock frequency