Datasheet

CHAPTER 14 SERIAL INTERFACE UART6
User’s Manual U18698EJ1V0UD
370
14.4.4 Calculation of baud rate
(1) Baud rate calculation expression
The baud rate can be calculated by the following expression.
• Baud rate = [bps]
f
XCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register
k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 4, 5, 6, ..., 255)
Table 14-4. Set Value of TPS63 to TPS60
Base Clock (fXCLK6) Selection
Note 1
TPS63 TPS62 TPS61 TPS60
f
PRS =
2 MHz
fPRS =
5 MHz
fPRS =
8 MHz
fPRS =
10 MHz
0 0 0 0 fPRS
Note 2
2 MHz 5 MHz 8 MHz 10 MHz
0 0 0 1 fPRS/2 1 MHz 2.5 MHz 4 MHz 5 MHz
0 0 1 0 fPRS/2
2
500 kHz 1.25 MHz 2 MHz 2.5 MHz
0 0 1 1 fPRS/2
3
250 kHz 625 kHz 1 MHz 1.25 MHz
0 1 0 0 fPRS/2
4
125 kHz 312.5 kHz 500 kHz 625 kHz
0 1 0 1 fPRS/2
5
62.5 kHz 156.25 kHz 250 kHz 312.5 kHz
0 1 1 0 fPRS/2
6
31.25 kHz 78.13 kHz 125 kHz 156.25 kHz
0 1 1 1 fPRS/2
7
15.625 kHz 39.06 kHz 62.5 kHz 78.13 kHz
1 0 0 0 fPRS/2
8
7.813 kHz 19.53 kHz 31.25 kHz 39.06 kHz
1 0 0 1 fPRS/2
9
3.906 kHz 9.77 kHz 15.625 kHz 19.53 kHz
1 0 1 0 fPRS/2
10
1.953 kHz 4.88 kHz 7.813 kHz 9.77 kHz
1 0 1 1 TM50 output
Note 3
Other than above Setting prohibited
Notes 1. If the peripheral hardware clock (f
PRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
• V
DD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• VDD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
2. If the peripheral hardware clock (f
PRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
= 0), when 1.8 V ≤ V
DD < 2.7 V, the setting of TPS63 = TPS62 = TPS61 = TPS60 = 0 (base clock: fPRS)
is prohibited.
3. When selecting the TM50 output as the base clock, Start the operation of 8-bit timer/event counter 50
first and then enable the timer F/F inversion operation (TMC501 = 1).
f
XCLK6
2 × k