Datasheet

CHAPTER 13 SERIAL INTERFACE UART0
User’s Manual U18698EJ1V0UD
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(2) Generation of serial clock
A serial clock to be generated can be specified by using baud rate generator control register 0 (BRGC0).
Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0.
Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value (f
XCLK0/8 to fXCLK0/31) of the 5-bit
counter.
13.4.4 Calculation of baud rate
(1) Baud rate calculation expression
The baud rate can be calculated by the following expression.
• Baud rate = [bps]
f
XCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits of the BRGC0 register
k: Value set by the MDL04 to MDL00 bits of the BRGC0 register (k = 8, 9, 10, ..., 31)
Table 13-4. Set Value of TPS01 and TPS00
Base clock (fXCLK0) selection
Note 1
TPS01 TPS00
f
PRS = 2 MHz fPRS = 5 MHz fPRS = 8 MHz fPRS = 10 MHz
0 0 TM50 output
Note 2
0 1 fPRS/2 1 MHz 2.5 MHz 4 MHz 5 MHz
1 0 fPRS/2
3
250 kHz 625 kHz 1 MHz 1.25 MHz
1 1 fPRS/2
5
62.5 kHz 156.25 kHz 250 kHz 312.5 kHz
Notes 1. If the peripheral hardware clock (f
PRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
f
PRS operating frequency varies depending on the supply voltage.
• V
DD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• V
DD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
2. When selecting the TM50 output as the base clock, start the operation of 8-bit timer/event counter 50
first and then enable the timer F/F inversion operation (TMC501 = 1).
(2) Error of baud rate
The baud rate error can be calculated by the following expression.
• Error (%) = − 1 × 100 [%]
f
XCLK0
2 × k
Actual baud rate (baud rate with error)
Desired baud rate (correct baud rate)