Datasheet

CHAPTER 13 SERIAL INTERFACE UART0
User’s Manual U18698EJ1V0UD
320
(3) Baud rate generator control register 0 (BRGC0)
This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter.
BRGC0 can be set by an 8-bit memory manipulation instruction.
Reset signal generation sets this register to 1FH.
Figure 13-4. Format of Baud Rate Generator Control Register 0 (BRGC0)
Address: FF71H After reset: 1FH R/W
Symbol 7 6 5 4 3 2 1 0
BRGC0 TPS01 TPS00 0 MDL04 MDL03 MDL02 MDL01 MDL00
Base clock (fXCLK0) selection
Note 1
TPS01 TPS00
fPRS = 2 MHz fPRS = 5 MHz fPRS = 8 MHz fPRS = 10 MHz
0 0 TM50 output
Note 2
0 1 fPRS/2 1 MHz 2.5 MHz 4 MHz 5 MHz
1 0 fPRS/2
3
250 kHz 625 kHz 1 MHz 1.25 MHz
1 1 fPRS/2
5
62.5 kHz 156.25 kHz 250 kHz 312.5 kHz
MDL04 MDL03 MDL02 MDL01 MDL00 k Selection of 5-bit counter
output clock
0 0
× × × ×
Setting prohibited
0 1 0 0 0 8 fXCLK0/8
0 1 0 0 1 9 fXCLK0/9
0 1 0 1 0 10 fXCLK0/10
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1 1 0 1 0 26 fXCLK0/26
1 1 0 1 1 27 fXCLK0/27
1 1 1 0 0 28 fXCLK0/28
1 1 1 0 1 29 fXCLK0/29
1 1 1 1 0 30 fXCLK0/30
1 1 1 1 1 31 fXCLK0/31
Notes 1. If the peripheral hardware clock (fPRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
f
PRS operating frequency varies depending on the supply voltage.
• V
DD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• V
DD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
2. When selecting the TM50 output as the base clock, Start the operation of 8-bit timer/event counter 50
first and then enable the timer F/F inversion operation (TMC501 = 1).
Cautions 1. Make sure that bit 6 (TXE0) and bit 5 (RXE0) of the ASIM0 register = 0 when rewriting the
MDL04 to MDL00 bits.
2. The baud rate value is the output clock of the 5-bit counter divided by 2.