Datasheet

CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER ( μ PD78F041x only)
User’s Manual U18698EJ1V0UD
295
Figure 12-4. Timing Chart When Comparator Is Used
ADCE
Comparator
ADCS
Conversion
operation
Conversion
operation
Conversion
stopped
Conversion
waiting
Comparator operation
Note
Note To stabilize the internal circuit, the time from the rising of the ADCE bit to the falling of the ADCS bit must be
1
μ s or longer.
Cautions 1. A/D conversion must be stopped before rewriting bits FR0 to FR3, LV1, and LV0 to values
other than the identical data.
2. If data is written to ADM, a wait cycle is generated. Do not write data to ADM when the CPU is
operating on the subsystem clock and the peripheral hardware clock is stopped. For details,
see CHAPTER 29 CAUTIONS FOR WAIT.