Datasheet

CHAPTER 11 BUZZER OUTPUT CONTROLLER
User’s Manual U18698EJ1V0UD
289
Figure 11-2. Format of Clock Output Selection Register (CKS)
Address: FF40H After reset: 00H R/W
Symbol <7> 6 5 4 3 2 1 0
CKS BZOE BCS1 BCS0 0 0 0 0 0
BZOE BUZ output enable/disable specification
0 Clock division circuit operation stopped. BUZ fixed to low level.
1 Clock division circuit operation enabled. BUZ output enabled.
BUZ output clock selection BCS1 BCS0
f
PRS = 5 MHz fPRS = 10 MHz
0 0 fPRS/2
10
4.88 kHz 9.77 kHz
0 1 fPRS/2
11
2.44 kHz 4.88 kHz
1 0 fPRS/2
12
1.22 kHz 2.44 kHz
1 1 fPRS/2
13
0.61 kHz 1.22 kHz
Caution Set BCS1 and BCS0 when the buzzer output operation is stopped (BZOE = 0).
Remark f
PRS: Peripheral hardware clock frequency