Datasheet

CHAPTER 11 BUZZER OUTPUT CONTROLLER
User’s Manual U18698EJ1V0UD
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11.2 Configuration of Buzzer Output Controller
The buzzer output controller includes the following hardware.
Table 11-1. Configuration of Buzzer Output Controller
Item Configuration
Control registers Clock output selection register (CKS)
Port mode register 3 (PM3)
Port register 3 (P3)
11.3 Registers Controlling Buzzer Output Controller
The following two registers are used to control the buzzer output controller.
• Clock output selection register (CKS)
• Port mode register 3 (PM3)
(1) Clock output selection register (CKS)
This register sets output enable/disable for the buzzer frequency output (BUZ), and sets the output clock.
CKS is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears CKS to 00H.