Datasheet
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2
User’s Manual U18698EJ1V0UD
244
Figure 8-8. Format of 8-Bit Timer H Mode Register 2 (TMHMD2)
TMHE2
Stops timer count operation (counter is cleared to 0)
Enables timer count operation (count operation started by inputting clock)
TMHE2
0
1
Timer operation enable
TMHMD2 CKS22 CKS21 CKS20 TMMD21 TMMD20 TOLEV2 TOEN2
Address: FF42H After reset: 00H R/W
Interval timer mode
Input enable width adjust mode for pins (PWM mode)
TMMD21
0
1
TMMD20
0
0
Timer operation mode
Low level
High level
TOLEV2
0
1
Timer output level control (in default mode)
Disables output
Enables output
Note 3
TOEN2
0
1
Timer output control
<7>
6
5
4
3 2 <1>
<0>
CKS22
0
0
0
0
1
1
1
CKS21
0
0
1
1
0
0
1
CKS20
0
1
0
1
0
1
0
Count clock selection
Note 1
Setting prohibited
Other than above
Setting prohibited
Other than above
f
PRS
Note 2
f
PRS
/2
f
PRS
/2
2
f
PRS
/2
4
f
PRS
/2
6
f
PRS
/2
10
f
PRS
/2
12
f
PRS
=
2 MHz
2 MHz
1 MHz
500 kHz
125 kHz
31.25 kHz
1.95 kHz
0.49 kHz
f
PRS
=
5 MHz
5 MHz
2.5 MHz
1.25 MHz
312.5 kHz
78.13 kHz
4.88 kHz
1.22 kHz
f
PRS
=
10 MHz
10 MHz
5 MHz
2.5 MHz
625 kHz
156.25 kHz
9.77 kHz
2.44 kHz
Notes 1. If the peripheral hardware clock (f
PRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
• V
DD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• V
DD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
2. If the peripheral hardware clock (f
PRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
= 0), when 1.8 V ≤ V
DD < 2.7 V, the setting of CKS22 = CKS21 = CKS20 = 0 (count clock: fPRS) is
prohibited.
3. The timer output of TMH2 can only be used as an external event input enable signal of TM52. No pins
for external output are available.
Caution When TMHE2 = 1, setting the other bits of TMHMD2 is prohibited.
Remark f
PRS: Peripheral hardware clock frequency