Datasheet

CHAPTER 8 8-BIT TIMERS H0, H1, AND H2
User’s Manual U18698EJ1V0UD
242
Figure 8-7. Format of 8-Bit Timer H Mode Register 1 (TMHMD1)
TMHE1
Stops timer count operation (counter is cleared to 0)
Enables timer count operation (count operation started by inputting clock)
TMHE1
0
1
Timer operation enable
TMHMD1 CKS12 CKS11 CKS10 TMMD11 TMMD10 TOLEV1 TOEN1
Address: FF6CH After reset: 00H R/W
Interval timer mode
Carrier generator mode
PWM output mode
Setting prohibited
TMMD11
0
0
1
1
TMMD10
0
1
0
1
Timer operation mode
Low level
High level
TOLEV1
0
1
Timer output level control (in default mode)
Disables output
Enables output
TOEN1
0
1
Timer output control
<7>
6
5
4
3 2 <1>
<0>
f PRS
Note 2
f PRS /2
2
f PRS /2
4
f PRS /2
6
f PRS /2
12
f RL /2
7
f RL /2
9
f RL
CKS12
0
0
0
0
1
1
1
1
CKS11
0
0
1
1
0
0
1
1
CKS10
0
1
0
1
0
1
0
1
f
PRS =
2 MHz
2 MHz
500 kHz
125 kHz
31.25 kHz
0.49 kHz
1.88 kHz (TYP.)
0.47 kHz (TYP.)
240 kHz (TYP.)
Count clock selection
Note 1
f PRS =
5 MHz
5 MHz
1.25 MHz
312.5 kHz
78.13 kHz
1.22 kHz
f PRS =
10 MHz
10 MHz
2.5 MHz
625 kHz
156.25 kHz
2.44 kHz
Notes 1. If the peripheral hardware clock (f
PRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
f
PRS operating frequency varies depending on the supply voltage.
• V
DD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• V
DD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
2. If the peripheral hardware clock (f
PRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
= 0), when 1.8 V ≤ VDD < 2.7 V, the setting of CKS12 = CKS11 = CKS10 = 0 (count clock: fPRS) is
prohibited.