Datasheet

CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52
User’s Manual U18698EJ1V0UD
223
Figure 7-7. Format of Timer Clock Selection Register 51 (TCL51)
Address: FF8CH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
TCL51 0 0 0 0 0 TCL512 TCL511 TCL510
Count clock selection
Note1
TCL512 TCL511 TCL510
f
PRS =
2 MHz
fPRS =
5 MHz
fPRS =
10 MHz
0 0 0
0 0 1
Setting prohibited
0 1 0 fPRS
Note2
2 MHz 5 MHz 10 MHz
0 1 1 fPRS/2 1 MHz 2.5 MHz 5 MHz
1 0 0 fPRS/2
4
125 kHz 312.5 kHz 625 kHz
1 0 1 fPRS/2
6
31.25 kHz 78.13 kHz 156.25 kHz
1 1 0 fPRS/2
8
7.81 kHz 19.53 kHz 39.06 kHz
1 1 1 Timer H1 output signal
Notes 1. If the peripheral hardware clock (f
PRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
fPRS operating frequency varies depending on the supply voltage.
• VDD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• V
DD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
2. If the peripheral hardware clock (f
PRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
= 0), when 1.8 V ≤ V
DD < 2.7 V, the setting of TCL512, TCL511, TCL510 = 0, 1, 0 (count clock: fPRS) is
prohibited.
Cautions 1. When rewriting TCL51 to other data, stop the timer operation beforehand.
2. Be sure to clear bits 3 to 7 to 0.