Datasheet

CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
User’s Manual U18698EJ1V0UD
209
<3> When the TM52 and CR52 (= FFH) values match, TM52 is cleared to 00, and the match signal causes TM000
to start counting up. Then, when the TM000 and CR000 values match, TM00 is cleared to 0000H, and a
match interrupt signal (INTTM000) is generated.
If input enable for the TI52 pin is controlled, external event count values within the input enable periods for the
TI52 pin can be measured, by reading TM52, the TM00 count value, and TMIF52 via interrupt servicing by the
TMH2 interrupt request signal (INTTMH2).
Figure 6-55. Operation Timing of External 24-bit Event Counter
TMH2 output signal
Clear TM52/TM00 counter
Read TM52/TM00 count value
TI52
TM52
TM00
INTTM52
INTTMH2
TI52 & TOH2
41H
1234H 0000H 0001H 0000H 0001H0002H FFFEH FFFFH
42H 43H FFH 00H 01H FFH 00H 01H FFH 00H 01H FFH 00H 01H FFH 00H 01H00H 01H02H 03H 04H00H 01H
Clear TM52/TM00 counter
Read TM52/TM00 count value