Datasheet

CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
User’s Manual U18698EJ1V0UD
191
Figure 6-42. Example of Register Settings for PPG Output Operation
(a) 16-bit timer mode control register 00 (TMC00)
00001100
TMC003 TMC002 TMC001 OVF00
Clears and starts on match
between TM00 and CR000.
(b) Capture/compare control register 00 (CRC00)
00000000
CRC002 CRC001 CRC000
CR000 used as
compare register
CR010 used as
compare register
(c) 16-bit timer output control register 00 (TOC00)
0 0 0 1 0/1
LVR00LVS00TOC004OSPE00OSPT00 TOC001 TOE00
Enables TO00 output
11: Inverts TO00 output on
match between TM00
and CR000/CR010.
00: Disables one-shot pulse
output
Specifies initial value of
TO00 output F/F
0/1 1 1
(d) Prescaler mode register 00 (PRM00)
00000
3 PRM002 PRM001 PRM000ES101 ES100 ES001 ES000
Selects count clock
0/1 0/1 0/1
(e) 16-bit timer counter 00 (TM00)
By reading TM00, the count value can be read.
(f) 16-bit capture/compare register 000 (CR000)
An interrupt signal (INTTM000) is generated when the value of this register matches the count value of TM00.
The count value of TM00 is not cleared.
(g) 16-bit capture/compare register 010 (CR010)
An interrupt signal (INTTM010) is generated when the value of this register matches the count value of TM00.
The count value of TM00 is not cleared.
Caution Set values to CR000 and CR010 such that the condition 0000H ≤ CR010 < CR000 ≤ FFFFH is
satisfied.