Datasheet

CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
User’s Manual U18698EJ1V0UD
169
Figure 6-24. Timing Example of Clear & Start Mode Entered by TI000 Pin Valid Edge Input
(CR000: Compare Register, CR010: Compare Register)
(a) TOC00 = 13H, PRM00 = 10H, CRC00, = 00H, TMC00 = 08H
TM00 register
0000H
Operable bits
(TMC003, TMC002)
Count clear input
(TI000 pin input)
Compare register
(CR000)
Compare match interrupt
(INTTM000)
Compare register
(CR010)
Compare match interrupt
(INTTM010)
TO00 output
M
10
M
NN NN
MMM
00
N
(b) TOC00 = 13H, PRM00 = 10H, CRC00, = 00H, TMC00 = 0AH
TM00 register
0000H
Operable bits
(TMC003, TMC002)
Count clear input
(TI000 pin input)
Compare register
(CR000)
Compare match interrupt
(INTTM000)
Compare register
(CR010)
Compare match interrupt
(INTTM010)
TO00 output
M
10
M
NN NN
MMM
00
N
(a) and (b) differ as follows depending on the setting of bit 1 (TMC001) of the 16-bit timer mode control register 01
(TMC00).
(a) The TO00 output level is inverted when TM00 matches a compare register.
(b) The TO00 output level is inverted when TM00 matches a compare register or when the valid edge of the
TI000 pin is detected.