Datasheet

CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00
User’s Manual U18698EJ1V0UD
155
Figure 6-9. Format of Prescaler Mode Register 00 (PRM00)
Address: FFBBH After reset: 00H R/W
Symbol 7 6 5 4 3 2 1 0
PRM00 ES101 ES100 ES001 ES000 0 PRM002 PRM001 PRM000
ES101 ES100 TI010 pin valid edge selection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohibited
1 1 Both falling and rising edges
ES001 ES000 TI000 pin valid edge selection
0 0 Falling edge
0 1 Rising edge
1 0 Setting prohibited
1 1 Both falling and rising edges
Count clock selection
Note1
PRM002 PRM001 PRM000
f
PRS = 2 MHz fPRS = 5 MHz fPRS = 10 MHz
0 0 0 fPRS
Note2
2 MHz 5 MHz 10 MHz
0 0 1 fPRS/2 1 MHz 2.5 MHz 5 MHz
0 1 0 fPRS/2
2
500 kHz 1.25 MHz 2.5 MHz
0 1 1 fPRS/2
4
1.25 MHz 2.5 MHz 625 kHz
1 0 0 fPRS/2
8
7.81 kHz 19.53 kHz 39.06 kHz
1 0 1 fSUB 32.768 kHz
1 1 0 TI000 valid edge
Note3
1 1 1 TM52 output
Notes 1. If the peripheral hardware clock (f
PRS) operates on the high-speed system clock (fXH) (XSEL = 1), the
f
PRS operating frequency varies depending on the supply voltage.
• V
DD = 2.7 to 5.5 V: fPRS ≤ 10 MHz
• VDD = 1.8 to 2.7 V: fPRS ≤ 5 MHz
2. If the peripheral hardware clock (f
PRS) operates on the internal high-speed oscillation clock (fRH) (XSEL
= 0), when 1.8 V ≤ V
DD < 2.7 V, the setting of PRM002 = PRM001 = PRM000 = 0 (count clock: fPRS) is
prohibited.
3. The external clock from the TI000 pin requires a pulse longer than twice the cycle of the peripheral
hardware clock (f
PRS).
Caution Do not select the valid edge of TI000 as the count clock during the pulse width measurement.
Remarks 1. 8-bit timer/event counter 52 (TM52) output can be selected as the TM00 count clock by setting
PRM002, PRM001, PRM000 = 1, 1, 1. Any frequency can be set as the 16-bit timer (TM00) count
clock, depending on the TM52 count clock and compare register setting values.
2. f
PRS: Peripheral hardware clock frequency
f
SUB: Subsystem clock frequency