Datasheet

CHAPTER 5 CLOCK GENERATOR
User’s Manual U18698EJ1V0UD
136
Table 5-5. CPU Clock Transition and SFR Register Setting Examples (2/4)
(4) CPU clock changing from internal high-speed oscillation clock (B) to high-speed system clock (C)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
EXCLK OSCSEL MSTOP
OSTC
Register
XSEL
Note
MCM0
(B) → (C) (X1 clock) 0 1 0
Must be
checked
1 1
(B) → (C) (external main clock) 1 1 0
Must not be
checked
1 1
Unnecessary if these
registers are already set
Unnecessary if the CPU
is operating with the
high-speed system clock
Note The value of this flag can be changed only once after a reset release. This setting is not necessary if it has
already been set.
Caution Set the clock after the supply voltage has reached the operable voltage of the clock to be set (see
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS)).
(5) CPU clock changing from internal high-speed oscillation clock (B) to subsystem clock (D)
(Setting sequence of SFR registers)
Setting Flag of SFR Register
Status Transition
OSCSELS
Waiting for Oscillation
Stabilization
CSS
(B) → (D) 1 Necessary 1
Remarks 1. (A) to (I) in Table 5-5 correspond to (A) to (I) in Figure 5-15.
2. EXCLK, OSCSEL, OSCSELS:
Bits 7, 6, and 4 of the clock operation mode select register (OSCCTL)
MSTOP: Bit 7 of the main OSC control register (MOC)
XSEL, MCM0: Bits 2 and 0 of the main clock mode register (MCM)
CSS: Bit 4 of the processor clock control register (PCC)