Datasheet

CHAPTER 5 CLOCK GENERATOR
User’s Manual U18698EJ1V0UD
134
5.6.6 CPU clock status transition diagram
Figure 5-15 shows the CPU clock status transition diagram of this product.
Figure 5-15. CPU Clock Status Transition Diagram
(When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0))
Power ON
Reset release
Internal low-speed oscillation: Woken up
Internal high-speed oscillation: Woken up
X1 oscillation/EXCLK input: Stops (I/O port mode)
XT1 oscillation input: Stops (Input port mode)
Internal low-speed oscillation: Operating
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input: Stops (I/O port mode)
XT1 oscillation input: Stops (Input port mode)
CPU: Operating
with internal high-
speed oscillation
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operating
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation input: Selectable by CPU
CPU: Internal high-
speed oscillation
→ STOP
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation input: Operable
CPU: Internal high-
speed oscillation
→ HALT
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operating
X1 oscillation/EXCLK input: Operable
XT1 oscillation input: Operable
CPU: Operating
with X1 oscillation or
EXCLK input
CPU: X1
oscillation/EXCLK
input → STOP
CPU: X1
oscillation/EXCLK
input → HALT
Internal low-speed oscillation: Operable
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input: Operating
XT1 oscillation input: Selectable by CPU
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Stops
X1 oscillation/EXCLK input: Stops
XT1 oscillation: Operable
Internal low-speed oscillation:
Operable
Internal high-speed oscillation:
Operable
X1 oscillation/EXCLK input: Operating
XT1 oscillation input: Operable
CPU: Operating
with XT1 oscillation
input
CPU: XT1
oscillation input
→ HALT
Internal low-speed oscillation: Operable
Internal high-speed oscillation:
Selectable by CPU
X1 oscillation/EXCLK input:
Selectable by CPU
XT1 oscillation input: Operating
Internal low-speed oscillation: Operable
Internal high-speed oscillation: Operable
X1 oscillation/EXCLK input: Operable
XT1 oscillation input: Operating
(B)
(A)
(C)
(D)
(E)
(F)
(G)
(H)
(I)
V DD ≥ 1.59 V (TYP.)
V
DD ≥ 1.8 V (MIN.)
V
DD < 1.59 V (TYP.)
Remark In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the CPU clock status changes to (A) in the
above figure when the supply voltage exceeds 2.7 V (TYP.), and to (B) after reset processing (11 to 47
μ s (TYP.)).