Datasheet

CHAPTER 5 CLOCK GENERATOR

User’s Manual U18698EJ1V0UD

114

(5) Main OSC control register (MOC)

This register selects the operation mode of the high-speed system clock.

This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the

CPU operates with a clock other than the high-speed system clock.

MOC can be set by a 1-bit or 8-bit memory manipulation instruction.

Reset signal generation sets this register to 80H.

Figure 5-5. Format of Main OSC Control Register (MOC)

Address: FFA2H After reset: 80H R/W

Symbol <7> 6 5 4 3 2 1 0

MOC MSTOP 0 0 0 0 0 0 0

Control of high-speed system clock operation

MSTOP

X1 oscillation mode External clock input mode

0 X1 oscillator operating External clock from EXCLK pin is enabled

1 X1 oscillator stopped External clock from EXCLK pin is disabled

Cautions 1. When setting MSTOP to 1, be sure to confirm that the CPU operates with a clock

other than the high-speed system clock. Specifically, set under either of the

following conditions.

• When MCS = 0 (when CPU operates with the internal high-speed oscillation

clock)

• When CLS = 1 (when CPU operates with the subsystem clock)

In addition, stop peripheral hardware that is operating on the high-speed system

clock before setting MSTOP to 1.

2. Do not clear MSTOP to 0 while bit 6 (OSCSEL) of the clock operation mode select

3. The peripheral hardware cannot operate when the peripheral hardware clock is

stopped. To resume the operation of the peripheral hardware after the

peripheral hardware clock has been stopped, initialize the peripheral hardware.