Datasheet

CHAPTER 5 CLOCK GENERATOR
User’s Manual U18698EJ1V0UD
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(2) Processor clock control register (PCC)
This register is used to select the CPU clock, the division ratio, and operation mode for subsystem clock.
PCC is set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation sets PCC to 01H.
Figure 5-3. Format of Processor Clock Control Register (PCC)
Address: FFFBH After reset: 01H R/W
Note
Symbol 7 6 <5> <4> 3 2 1 0
PCC 0
0 CLS CSS 0 PCC2 PCC1 PCC0
CLS CPU clock status
0 Main system clock
1 Subsystem clock
Note Bit 5 is read-only.
Caution Be sure to clear bits 3, 6, and 7 to “0”.
Remarks 1. f
XP: Main system clock oscillation frequency
2. f
SUB: Subsystem clock oscillation frequency
The fastest instruction can be executed in 2 clocks of the CPU clock in the 78K0/LC3. Therefore, the relationship
between the CPU clock (f
CPU) and the minimum instruction execution time is as shown in Table 5-2.
CSS PCC2 PCC1 PCC0 CPU clock (fCPU) selection
0 0 0 fXP
0 0 1 fXP/2 (default)
0 1 0 fXP/2
2
0 1 1 fXP/2
3
0
1 0 0 fXP/2
4
0 0 0
0 0 1
0 1 0
0 1 1
1
1 0 0
f
SUB/2
Other than above Setting prohibited