Datasheet

CHAPTER 5 CLOCK GENERATOR
User’s Manual U18698EJ1V0UD
110
Figure 5-2. Format of Clock Operation Mode Select Register (OSCCTL)
Address: FF9FH After reset: 00H R/W
Symbol <7> <6> 5 <4> 3 2 1 0
OSCCTL EXCLK OSCSEL 0
OSCSELS 0 0 0 0
EXCLK OSCSEL High-speed system clock
pin operation mode
P121/X1 pin P122/X2/EXCLK pin
0 0 Input port mode Input port
0 1 X1 oscillation mode Crystal/ceramic resonator connection
1 0 Input port mode Input port
1 1 External clock input
mode
Input port External clock input
Caution To change the value of EXCLK and OSCSEL, be sure to confirm that bit 7 (MSTOP)
of the main OSC control register (MOC) is 1 (the X1 oscillator stops or the external
clock from the EXCLK pin is disabled).
Be sure to clear bits 0 to 3, and 5 to “0”.
Remark f
XH: High-speed system clock oscillation frequency