Datasheet

CHAPTER 5 CLOCK GENERATOR
User’s Manual U18698EJ1V0UD
109
Remarks 1. fX: X1 clock oscillation frequency
2. f
RH: Internal high-speed oscillation clock frequency
3. fEXCLK: External main system clock frequency
4. f
XH: High-speed system clock frequency
5. f
XP: Main system clock frequency
6. f
PRS: Peripheral hardware clock frequency
7. f
CPU: CPU clock frequency
8. f
XT: XT1 clock oscillation frequency
9. fSUB: Subsystem clock frequency
10. f
RL: Internal low-speed oscillation clock frequency
5.3 Registers Controlling Clock Generator
The following eight registers are used to control the clock generator.
• Clock operation mode select register (OSCCTL)
• Processor clock control register (PCC)
• Internal oscillation mode register (RCM)
• Main OSC control register (MOC)
• Main clock mode register (MCM)
• Oscillation stabilization time counter status register (OSTC)
• Oscillation stabilization time select register (OSTS)
• Internal high-speed oscillation trimming register (HIOTRM)
(1) Clock operation mode select register (OSCCTL)
This register selects the operation modes of the high-speed system and subsystem clocks, and the gain of the
on-chip oscillator.
OSCCTL can be set by a 1-bit or 8-bit memory manipulation instruction.
Reset signal generation clears this register to 00H.