Datasheet

CHAPTER 5 CLOCK GENERATOR
User’s Manual U18698EJ1V0UD
108
Figure 5-1. Block Diagram of Clock Generator
Option byte
1: Cannot be stopped
0: Can be stopped
Internal oscillation
mode register
(RCM)
LSRSTOP RSTS RSTOP
Internal high-
speed oscillator
(8 MHz (TYP.))
Internal low-
speed oscillator
(240 kHz (TYP.))
Clock operation mode
select register
(OSCCTL)
OSCSELS
XT1/P123
XT2/P124
Peripheral
hardware
clock (f
PRS )
Watchdog timer,
8-bit timer H1,
LCD controller/driver
1/2
CPU clock
(f
CPU )
Processor clock
control register
(PCC)
CSS PCC2CLS PCC1 PCC0
Prescaler
Main system
clock switch
Peripheral
hardware
clock switch
X1 oscillation
stabilization time counter
OSTS1 OSTS0OSTS2
Oscillation stabilization
time select register (OSTS)
3
MOST
16
MOST
15
MOST
14
MOST
13
MOST
11
Oscillation
stabilization
time counter
status register
(OSTC)
Controller
MCM0 XSEL
MCS
MSTOP
EXCLK
OSCSEL
Clock operation mode
select register
(OSCCTL)
4
Main clock
mode register
(MCM)
Main clock
mode register
(MCM)
Main OSC
control register
(MOC)
Internal bus
Internal bus
High-speed system
clock oscillator
Crystal/ceramic
oscillation
External input
clock
X1/P121
X2/EXCLK/
P122
Crystal
oscillation
Subsystem
clock oscillator
Selector
STOP
Internal high-speed oscillation
trimming register (HIOTRM)
TTRM3 TTRM2TTRM4 TTRM1 TTRM0
5
f SUB
f RH
f XH
f X
f EXCLK
f XT
f RL
f XP
f XP
2
f
XP
2
2
f XP
2
3
f XP
2
4
f SUB
2