To our customers, Old Company Name in Catalogs and Other Documents On April 1st, 2010, NEC Electronics Corporation merged with Renesas Technology Corporation, and Renesas Electronics Corporation took over all the business of both companies. Therefore, although the old company name remains in this document, it is a valid Renesas Electronics document. We appreciate your understanding. Renesas Electronics website: http://www.renesas.
Notice 1. 2. 3. 4. 5. 6. 7. All information included in this document is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas Electronics products listed herein, please confirm the latest product information with a Renesas Electronics sales office.
User’s Manual 78K0/LC3 8-Bit Single-Chip Microcontrollers μPD78F0400 μPD78F0401 μPD78F0402 μPD78F0403 μPD78F0410 μPD78F0411 μPD78F0412 μPD78F0413 The 78K0/LC3 has an on-chip debug function. Do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, due to issues with respect to the number of times the flash memory can be rewritten. NEC Electronics does not accept complaints concerning this product. Document No.
[MEMO] 2 User’s Manual U18698EJ1V0UD
NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
EEPROM is a trademark of NEC Electronics Corporation. SuperFlash is a registered trademark of Silicon Storage Technology, Inc. in several countries including the United States and Japan. Caution: This product uses SuperFlash® technology licensed from Silicon Storage Technology, Inc. • The information in this document is current as of June, 2007. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc.
INTRODUCTION Readers This manual is intended for user engineers who wish to understand the functions of the 78K0/LC3 and design and develop application systems and programs for these devices. The target products are as follows. 78K0/LC3: μPD78F0400, 78F0401, 78F0402, 78F0403 μPD78F0410, 78F0411, 78F0412, 78F0413 Purpose This manual is intended to give users an understanding of the functions described in the Organization below.
Related Documents The related documents indicated in this publication may include preliminary versions. However, preliminary versions are not marked as such. Documents Related to Devices Document Name Document No. 78K0/LC3 User’s Manual This manual 78K/0 Series Instructions User’s Manual U12326E Documents Related to Flash Memory Programming Document Name Document No.
CONTENTS CHAPTER 1 OUTLINE ............................................................................................................................ 14 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Features ........................................................................................................................................ 14 Applications.................................................................................................................................. 15 Ordering Information ...........
3.3.1 Relative addressing......................................................................................................................... 64 3.3.2 Immediate addressing..................................................................................................................... 65 3.3.3 Table indirect addressing ................................................................................................................ 66 3.3.4 Register addressing .........................................
5.6.1 Example of controlling high-speed system clock ...........................................................................127 5.6.2 Example of controlling internal high-speed oscillation clock ..........................................................129 5.6.3 Example of controlling subsystem clock ........................................................................................131 5.6.4 Example of controlling internal low-speed oscillation clock.................................................
8.4.3 Carrier generator operation (8-bit timer H1 only)............................................................................255 CHAPTER 9 REAL-TIME COUNTER................................................................................................... 262 9.1 9.2 9.3 9.4 Functions of Real-Time Counter............................................................................................... 262 Configuration of Real-Time Counter ...............................................................
.4.4 Calculation of baud rate ...............................................................................................................331 CHAPTER 14 SERIAL INTERFACE UART6 ...................................................................................... 335 14.1 14.2 14.3 14.4 Functions of Serial Interface UART6...................................................................................... 335 Configuration of Serial Interface UART6 ....................................................
CHAPTER 18 KEY INTERRUPT FUNCTION ..................................................................................... 454 18.1 Functions of Key Interrupt ...................................................................................................... 454 18.2 Configuration of Key Interrupt ................................................................................................ 454 18.3 Register Controlling Key Interrupt ........................................................................
24.5.5 REGC pin.....................................................................................................................................515 24.5.6 Other signal pins ..........................................................................................................................516 24.5.7 Power supply ...............................................................................................................................516 24.6 Programming Method .................................
CHAPTER 1 OUTLINE 1.1 Features { Minimum instruction execution time can be changed from high speed (0.2 μs: @ 10 MHz operation with highspeed system clock) to ultra low-speed (122 μs: @ 32.
CHAPTER 1 OUTLINE 1.2 Applications Digital cameras, AV equipments, household electrical appliances, utility meters, health care equipments, and measurement equipment, etc. 1.
CHAPTER 1 OUTLINE 1.
CHAPTER 1 OUTLINE (2) μPD78F0410, 78F0411, 78F0412, 78F0413 P12/RxD0/KR3/ P13/TxD0/KR4/ P34/TI52/TI010/TO00/RTC1HZ/INTP1 P33/TI000/RTCDIV/RTCCL/BUZ/INTP2 P32/TOH0/MCGO P31/TOH1/INTP3 P20/SEG21/ANI0 P21/SEG20/ANI1 P22/SEG19/ANI2 P23/SEG18/ANI3 P24/SEG17/ANI4 P25/SEG16/ANI5 • 48-pin plastic LQFP (fine pitch) (7 × 7) 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 AVSS AVREF COM0 COM1 COM2 COM3 COM4/SEG0 CO
CHAPTER 1 OUTLINE Pin Identification ANI0 to ANI5Note: Analog input P150 to P153: Port 15 AVREFNote: Analog reference voltage REGC Regulator capacitance AVSSNote: Analog ground RESET: Reset BUZ: Buzzer output RxD0, RxD6: Receive data COM0 to COM7: Common output RTC1HZ: EXCLK: External clock input EXLVI: External potential input FLMD0: Flash programming mode INTP0 to INTP3: External interrupt input SEG0 to SEG21: Segment output KR0, KR3, KR4: Key return TI000, TI010: Timer in
CHAPTER 1 OUTLINE 1.
CHAPTER 1 OUTLINE The list of functions in the 78K0/Lx3 Microcontrollers is shown below. μPD78F040x Item 78K0/LD3 μPD78F041x RAM (KB) 8 16 24 32 8 16 24 32 8 16 24 32 8 16 24 32 0.5 0.75 1 1 0.5 0.75 1 1 0.5 0.75 1 1 0.5 0.75 1 1 VDD = 1.8 to 5.5 V Regulator Provided 0.2 μs (10 MHz: VDD = 2.7 to 5.5 V)/ 0.4 μs (5 MHz: VDD = 1.8 to 5.5 V) Main Clock Minimum instruction execution time High-speed system clock 10 MHz: VDD = 2.7 to 5.5 V/5 MHz: VDD = 1.8 to 5.
CHAPTER 1 OUTLINE (2/3) 78K0/LE3 Part Number μPD78F044x μPD78F045x Item Flash memory (KB) RAM (KB) 16 24 32 48 60 16 24 32 48 60 16 24 32 48 60 0.75 1 1 2 2 0.75 1 1 2 2 0.75 1 1 2 2 Power supply voltage VDD = 1.8 to 5.5 V Regulator Provided 0.2 μs (10 MHz: VDD = 2.7 to 5.5 V)/ 0.4 μs (5 MHz: VDD = 1.8 to 5.5 V) Main Clock Minimum instruction execution time High-speed system clock 10 MHz: VDD = 2.7 to 5.5 V/5 MHz: VDD = 1.8 to 5.
CHAPTER 1 OUTLINE (3/3) 78K0/LF3 Part Number μPD78F047x μPD78F048x Item Flash memory (KB) RAM (KB) 16 24 32 48 60 16 24 32 48 60 16 24 32 48 60 0.75 1 1 2 2 0.75 1 1 2 2 0.75 1 1 2 2 Power supply voltage VDD = 1.8 to 5.5 V Regulator Provided 0.2 μs (10 MHz: VDD = 2.7 to 5.5 V)/ 0.4 μs (5 MHz: VDD = 1.8 to 5.5 V) Main Clock Minimum instruction execution time High-speed system clock 10 MHz: VDD = 2.7 to 5.5 V/5 MHz: VDD = 1.8 to 5.
CHAPTER 1 OUTLINE 1.
CHAPTER 1 OUTLINE 1.
CHAPTER 1 OUTLINE (2/2) Item μPD78F0400 μPD78F0401 μPD78F0402 μPD78F0403 μPD78F0410 μPD78F0411 μPD78F0412 μPD78F0413 10-bit successive approximation • μPD78F040x: None type A/D converter • μPD78F041x: 6 channels Note 1 Serial interface • UART supporting LIN-bus • UART: 1 channel : 1 channel LCD controller/driver • External resistance division and internal resistance division are switchable.
CHAPTER 1 OUTLINE An outline of the timer is shown below.
CHAPTER 2 PIN FUNCTIONS 2.1 Pin Function List There are three types of pin I/O buffer power supplies: AVREFNote, VLC0, and VDD. The relationship between these power supplies and the pins is shown below. Table 2-1. Pin I/O Buffer Power Supplies Power Supply AVREF Note Note Corresponding Pins P20 to P25 VLC0 COM0 to COM7, SEG0 to SEG21, VLC0 to VLC3 VDD Pins other than above μPD78F041x only. The power supply is VDD with μPD78F040x. (1) Port pins (1/2) Function Name P12 I/O I/O Function Port 1.
CHAPTER 2 PIN FUNCTIONS (1) Port pins (2/2) Function Name P100, P101 I/O I/O Function Port 10. After Reset Input port Alternate Function SEG4, SEG5 2-bit I/O port. Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. P112 I/O Port 11. Input port 2-bit I/O port. P113 SEG6/TxD6 SEG7/RxD6 Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting.
CHAPTER 2 PIN FUNCTIONS (2) Non-port pins Function Name (1/2) I/O Function After Reset Alternate Function ANI0 Note ANI1 Note ANI2 Note P22/SEG19 ANI3 Note P23/SEG18 ANI4 Note P24/SEG17 ANI5 Note P25/SEG16 AVREF Input Note Input 10-bit successive approximation type A/D converter Digital input P20/SEG21 analog input.
CHAPTER 2 PIN FUNCTIONS (2) Non-port pins Function Name (2/2) I/O Function After Reset Alternate Function − − RESET Input System reset input RTCDIV Output Real-time counter clock (32 kHz divided frequency) output Input port RTCCL Output Real-time counter clock (32 kHz original oscillation) output Input port P33/TI000/RTCCL /BUZ/INTP2 P33/TI000/RTCDIV /BUZ/INTP2 RTC1HZ Output Real-time counter clock (1 Hz) output Input port P34/TI52/TI010/ TO00/INTP1 RxD0 Input Serial data input to
CHAPTER 2 PIN FUNCTIONS 2.2 Description of Pin Functions 2.2.1 P12, P13 (port 1) P12 and P13 function as a 2-bit I/O port. These pins also function as pins for key interrupt and serial interface data I/O. P13 can be selected to function as pins, using port function register 1 (PF1) (see Figure 4-19). The following operation modes can be specified in 1-bit units. (1) Port mode P12 and P13 function as a 2-bit I/O port.
CHAPTER 2 PIN FUNCTIONS 2.2.3 P31 to P34 (port 3) P31 to P34 function as a 4-bit I/O port. These pins also function as pins for external interrupt request input, timer I/O, buzzer output, real-time counter output, and manchester code output. The following operation modes can be specified in 1-bit units. (1) Port mode P31 to P34 function as a 4-bit I/O port. P31 to P34 can be set to input or output port in 1-bit units using port mode register 3 (PM3).
CHAPTER 2 PIN FUNCTIONS 2.2.4 P40 (port 4) P40 functions as a 1-bit I/O port. These pins also function as pins for key interrupt input and power supply voltage for driving the LCD. The following operation modes can be specified in 1-bit units. (1) Port mode P40 functions as a 1-bit I/O port. P40 can be set to input port or output port in 1-bit units using port mode register 4 (PM4). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 4 (PU4).
CHAPTER 2 PIN FUNCTIONS (a) SEG6, SEG7 These pins are the segment signal output pins for the LCD controller/driver. (b) RxD6 This is a serial data input pin of serial interface UART6. (c) TxD6 This is a serial data output pin of serial interface UART6. 2.2.7 P120 to P124 (port 12) P120 functions as a 1-bit I/O port. P121 to P124 function as a 4-bit input port.
CHAPTER 2 PIN FUNCTIONS (1) Port mode P140 to P143 function as a 4-bit I/O port. P140 to P143 can be set to input or output port in 1-bit units using port mode register 14 (PM14). Use of an on-chip pull-up resistor can be specified by pull-up resistor option register 14 (PU14). (2) Control mode P140 to P143 function as segment signal output pins for the LCD controller/driver. (a) SEG8 to SEG11 These pins are the segment signal output pins for the LCD controller/driver. 2.2.
CHAPTER 2 PIN FUNCTIONS 2.2.15 REGC This is the pin for connecting regulator output (2.4 V) stabilization capacitance for internal operation. Connect this pin to VSS via a capacitor (0.47 to 1 μF: recommended). REGC VSS Caution Keep the wiring length as short as possible in the area enclosed by the broken lines in the above figures. 2.2.16 VDD This is the positive power supply pin. 2.2.17 VSS This is the ground potential pin. 2.2.18 FLMD0 This is a pin for setting flash memory programming mode.
CHAPTER 2 PIN FUNCTIONS 2.3 Pin I/O Circuits and Recommended Connection of Unused Pins Table 2-2 shows the types of pin I/O circuits and the recommended connections of unused pins. See Figure 2-1 for the configuration of the I/O circuit of each type. Table 2-2. Pin I/O Circuit Types (1/2) Pin Name I/O Circuit Type P12/RxD0/KR3/ 5-AH Notes 1, 2 to P25/SEG16/ANI5 I/O Recommended Connection of Unused Pins Input: Independently connect to VDD or VSS via a resistor. Output: Leave open.
CHAPTER 2 PIN FUNCTIONS Table 2-2. Pin I/O Circuit Types (2/2) Pin Name P120/INTP0/EXLVI I/O Circuit Type I/O Recommended Connection of Unused Pins 5-AH I/O Input: Independently connect to VDD or VSS via a resistor. 37-A Input Independently connect to VDD or VSS via a resistor. 17-P I/O Output: Leave open. P121/X1/OCD0A Note 1 P122/X2/EXCLK/ OCD0B Note 1 P123/XT1 Note 1 P124/XT2 Note 1 P140/SEG8 to Independently connect to VDD or VSS via a resistor.
CHAPTER 2 PIN FUNCTIONS Figure 2-1.
CHAPTER 2 PIN FUNCTIONS Figure 2-1.
CHAPTER 3 CPU ARCHITECTURE 3.1 Memory Space Each products in the 78K0/LC3 can access a 64 KB memory space. Figures 3-1 to 3-4 show the memory maps. Caution Regardless of the internal memory capacity, the initial values of the internal memory size switching register (IMS) of all products in the 78K0/LC3 are fixed (IMS = CFH). Therefore, set the value corresponding to each product as indicated below. Table 3-1.
CHAPTER 3 CPU ARCHITECTURE Figure 3-1.
CHAPTER 3 CPU ARCHITECTURE Figure 3-2.
CHAPTER 3 CPU ARCHITECTURE Figure 3-3.
CHAPTER 3 CPU ARCHITECTURE Figure 3-4.
CHAPTER 3 CPU ARCHITECTURE Correspondence between the address values and block numbers in the flash memory are shown below. Table 3-2.
CHAPTER 3 CPU ARCHITECTURE 3.1.1 Internal program memory space The internal program memory space stores the program and table data. Normally, it is addressed with the program counter (PC). 78K0/LC3 products incorporate internal ROM (flash memory), as shown below. Table 3-3.
CHAPTER 3 CPU ARCHITECTURE (2) CALLT instruction table area The 64-byte area 0040H to 007FH can store the subroutine entry address of a 1-byte call instruction (CALLT). (3) Option byte area A 5-byte area of 0080H to 0084H and 1080H to 1084H can be used as an option byte area. Set the option byte at 0080H to 0084H when the boot swap is not used, and at 0080H to 0084H and 1080H to 1084H when the boot swap is used. For details, see CHAPTER 23 OPTION BYTE.
CHAPTER 3 CPU ARCHITECTURE 3.1.2 Internal data memory space 78K0/LC3 products incorporate the following RAMs. (1) Internal high-speed RAM Table 3-5. Internal High-Speed RAM Capacity Part Number Internal High-Speed RAM μPD78F0400, 78F0410 512 × 8 bits (FD00H to FEFFH) μPD78F0401, 78F0411 768 × 8 bits (FC00H to FEFFH) μPD78F0402, 78F0412 1024 × 8 bits (FB00H to FEFFH) μPD78F0403, 78F0413 This area cannot be used as a program area in which instructions are written and executed.
CHAPTER 3 CPU ARCHITECTURE 3.1.4 Data memory addressing Addressing refers to the method of specifying the address of the instruction to be executed next or the address of the register or memory relevant to the execution of instructions. Several addressing modes are provided for addressing the memory relevant to the execution of instructions for the 78K0/LC3, based on operability and other considerations.
CHAPTER 3 CPU ARCHITECTURE Figure 3-6.
CHAPTER 3 CPU ARCHITECTURE Figure 3-7.
CHAPTER 3 CPU ARCHITECTURE Figure 3-8.
CHAPTER 3 CPU ARCHITECTURE 3.2 Processor Registers The 78K0/LC3 products incorporate the following processor registers. 3.2.1 Control registers The control registers control the program sequence, statuses and stack memory. The control registers consist of a program counter (PC), a program status word (PSW) and a stack pointer (SP). (1) Program counter (PC) The program counter is a 16-bit register that holds the address information of the next program to be executed.
CHAPTER 3 CPU ARCHITECTURE (b) Zero flag (Z) When the operation result is zero, this flag is set (1). It is reset (0) in all other cases. (c) Register bank select flags (RBS0 and RBS1) These are 2-bit flags to select one of the four register banks. In these flags, the 2-bit information that indicates the register bank selected by SEL RBn instruction execution is stored. (d) Auxiliary carry flag (AC) If the operation result has a carry from bit 3 or a borrow at bit 3, this flag is set (1).
CHAPTER 3 CPU ARCHITECTURE Figure 3-12.
CHAPTER 3 CPU ARCHITECTURE Figure 3-13.
CHAPTER 3 CPU ARCHITECTURE 3.2.2 General-purpose registers General-purpose registers are mapped at particular addresses (FEE0H to FEFFH) of the data memory. The general-purpose registers consists of 4 banks, each bank consisting of eight 8-bit registers (X, A, C, B, E, D, L, and H). Each register can be used as an 8-bit register, and two 8-bit registers can also be used in a pair as a 16-bit register (AX, BC, DE, and HL).
CHAPTER 3 CPU ARCHITECTURE 3.2.3 Special function registers (SFRs) Unlike a general-purpose register, each special function register has a special function. SFRs are allocated to the FF00H to FFFFH areas in the CPU, and are allocated to the 00H to 03H areas of LCDCTL in the LCD controller/driver. Special function registers can be manipulated like general-purpose registers, using operation, transfer, and bit manipulation instructions.
CHAPTER 3 CPU ARCHITECTURE Table 3-6.
CHAPTER 3 CPU ARCHITECTURE Table 3-6.
CHAPTER 3 CPU ARCHITECTURE Table 3-6.
CHAPTER 3 CPU ARCHITECTURE Table 3-6.
CHAPTER 3 CPU ARCHITECTURE 3.3 Instruction Address Addressing An instruction address is determined by contents of the program counter (PC), and is normally incremented (+1 for each byte) automatically according to the number of bytes of an instruction to be fetched each time another instruction is executed.
CHAPTER 3 CPU ARCHITECTURE 3.3.2 Immediate addressing [Function] Immediate data in the instruction word is transferred to the program counter (PC) and branched. This function is carried out when the CALL !addr16 or BR !addr16 or CALLF !addr11 instruction is executed. CALL !addr16 and BR !addr16 instructions can be branched to the entire memory space. The CALLF !addr11 instruction is branched to the 0800H to 0FFFH area.
CHAPTER 3 CPU ARCHITECTURE 3.3.3 Table indirect addressing [Function] Table contents (branch destination address) of the particular location to be addressed by bits 1 to 5 of the immediate data of an operation code are transferred to the program counter (PC) and branched. This function is carried out when the CALLT [addr5] instruction is executed. This instruction references the address stored in the memory table from 40H to 7FH, and allows branching to the entire memory space.
CHAPTER 3 CPU ARCHITECTURE 3.4 Operand Address Addressing The following methods are available to specify the register and memory (addressing) to undergo manipulation during instruction execution. 3.4.1 Implied addressing [Function] The register that functions as an accumulator (A and AX) among the general-purpose registers is automatically (implicitly) addressed. Of the 78K0/LC3 instruction words, the following instructions employ implied addressing.
CHAPTER 3 CPU ARCHITECTURE 3.4.2 Register addressing [Function] The general-purpose register to be specified is accessed as an operand with the register bank select flags (RBS0 to RBS1) and the register specify codes of an operation code. Register addressing is carried out when an instruction with the following operand format is executed. When an 8-bit register is specified, one of the eight registers is specified with 3 bits in the operation code.
CHAPTER 3 CPU ARCHITECTURE 3.4.3 Direct addressing [Function] The memory to be manipulated is directly addressed with immediate data in an instruction word becoming an operand address.
CHAPTER 3 CPU ARCHITECTURE 3.4.4 Short direct addressing [Function] The memory to be manipulated in the fixed space is directly addressed with 8-bit data in an instruction word. This addressing is applied to the 256-byte space FE20H to FF1FH. Internal high-speed RAM and special function registers (SFRs) are mapped at FE20H to FEFFH and FF00H to FF1FH, respectively. The SFR area (FF00H to FF1FH) where short direct addressing is applied is a part of the overall SFR area.
CHAPTER 3 CPU ARCHITECTURE 3.4.5 Special function register (SFR) addressing [Function] A memory-mapped special function register (SFR) is addressed with 8-bit immediate data in an instruction word. This addressing is applied to the 240-byte spaces FF00H to FFCFH and FFE0H to FFFFH. However, the SFRs mapped at FF00H to FF1FH can be accessed with short direct addressing.
CHAPTER 3 CPU ARCHITECTURE 3.4.6 Register indirect addressing [Function] Register pair contents specified by a register pair specify code in an instruction word and by a register bank select flag (RBS0 and RBS1) serve as an operand address for addressing the memory. This addressing can be carried out for all of the memory spaces.
CHAPTER 3 CPU ARCHITECTURE 3.4.7 Based addressing [Function] 8-bit immediate data is added as offset data to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the offset data as a positive number to 16 bits. A carry from the 16th bit is ignored. This addressing can be carried out for all of the memory spaces.
CHAPTER 3 CPU ARCHITECTURE 3.4.8 Based indexed addressing [Function] The B or C register contents specified in an instruction word are added to the contents of the base register, that is, the HL register pair in the register bank specified by the register bank select flag (RBS0 and RBS1), and the sum is used to address the memory. Addition is performed by expanding the B or C register contents as a positive number to 16 bits. A carry from the 16th bit is ignored.
CHAPTER 3 CPU ARCHITECTURE 3.4.9 Stack addressing [Function] The stack area is indirectly addressed with the stack pointer (SP) contents. This addressing method is automatically employed when the PUSH, POP, subroutine call and return instructions are executed or the register is saved/reset upon generation of an interrupt request. With stack addressing, only the internal high-speed RAM area can be accessed.
CHAPTER 4 PORT FUNCTIONS 4.1 Port Functions There are two types of pin I/O buffer power supplies: AVREFNote and VDD. The relationship between these power supplies and the pins is shown below. Table 4-1. Pin I/O Buffer Power Supplies Power Supply AVREF VDD Note Note Corresponding Pins P20 to P25 Port pins other than P20 to P25 μPD78F041x only. The power supply is VDD with μPD78F040x. 78K0/LC3 products are provided with the ports shown in Figure 4-1, which enable variety of control operations.
CHAPTER 4 PORT FUNCTIONS Table 4-2. Port Functions Function Name P12 I/O I/O Function Port 1. After Reset Input port 2-bit I/O port. P13 Alternate Function RxD0/KR3/ TxD0/KR4/ Input/output can be specified in 1-bit units. Use of an on-chip pull-up resistor can be specified by a software setting. I/O P20 P21 Digital SEG21/ANI0 6-bit I/O port. input port SEG20/ANI1 Input/output can be specified in 1-bit units. P22 Note Port 2.
CHAPTER 4 PORT FUNCTIONS 4.2 Port Configuration Ports include the following hardware. Table 4-3.
CHAPTER 4 PORT FUNCTIONS 4.2.1 Port 1 Port 1 is a 2-bit I/O port with an output latch. Port 1 can be set to the input mode or output mode in 1-bit units using port mode register 1 (PM1). When the P12 and P13 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 1 (PU1). This port can also be used for key interrupt input and serial interface data I/O. Reset signal generation sets port 1 to input mode.
CHAPTER 4 PORT FUNCTIONS Figure 4-3.
CHAPTER 4 PORT FUNCTIONS 4.2.2 Port 2 Port 2 is a 6-bit I/O port with an output latch. Port 2 can be set to the input mode or output mode in 1-bit units using port mode register 2 (PM2). This port can also be used for 10-bit successive approximation type A/D converter analog input (μPD78F041x only) and segment output.
CHAPTER 4 PORT FUNCTIONS Figure 4-4. Block Diagram of P20 to P25 VDD WRPU PU2 PU20 to PU25 A/D converter P-ch Note Selector WRPORT P2 Selector Internal bus RD Output latch (P20 to P25) WRPM PM2 PM20 to PM25 LCD controller/driver WRPF PF2 PF20 to PF25 Note μPD78F041x only.
CHAPTER 4 PORT FUNCTIONS 4.2.3 Port 3 Port 3 is a 4-bit I/O port with an output latch. Port 3 can be set to the input mode or output mode in 1-bit units using port mode register 3 (PM3). When the P31 to P34 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 3 (PU3). This port can also be used for external interrupt request input, timer I/O, manchester code generator output, realtime counter output, and buzzer output.
CHAPTER 4 PORT FUNCTIONS Figure 4-6.
CHAPTER 4 PORT FUNCTIONS 4.2.4 Port 4 Port 4 is a 1-bit I/O port with an output latch. Port 4 can be set to the input mode or output mode in 1-bit units using port mode register 4 (PM4). When the P40 pin is used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 4 (PU4). This port can also be used for power supply voltage pins for driving the LCD and key interrupt input pin. Reset signal generation sets port 4 to input mode.
CHAPTER 4 PORT FUNCTIONS 4.2.5 Port 10 Port 10 is a 2-bit I/O port with an output latch. Port 10 can be set to the input mode or output mode in 1-bit units using port mode register 10 (PM10). When the P100 and P101 pins are used as an input port, use of an on-chip pullup resistor can be specified in 1-bit units by pull-up resistor option register 10 (PU10). This port can also be used for segment output. Reset signal generation sets port 10 to input mode. Figure 4-8 shows a block diagram of port 10.
CHAPTER 4 PORT FUNCTIONS 4.2.6 Port 11 Port 11 is a 2-bit I/O port with an output latch. Port 11 can be set to the input mode or output mode in 1-bit units using port mode register 11 (PM11). When the P112, P113 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 11 (PU11). This port can also be used for segment output and serial interface data I/O. Reset signal generation sets port 11 to input mode.
CHAPTER 4 PORT FUNCTIONS Figure 4-10.
CHAPTER 4 PORT FUNCTIONS 4.2.7 Port 12 Port 12 is a 1-bit I/O port with an output latch and a 4-bit input port. Only P120 can be set to the input mode or output mode in 1-bit units using port mode register 12 (PM12). When used as an input port only for P120, use of an on-chip pull-up resistor can be specified by pull-up resistor option register 12 (PU12).
CHAPTER 4 PORT FUNCTIONS Figure 4-11.
CHAPTER 4 PORT FUNCTIONS Figure 4-12.
CHAPTER 4 PORT FUNCTIONS Figure 4-13.
CHAPTER 4 PORT FUNCTIONS 4.2.8 Port 14 Port 14 is a 4-bit I/O port with an output latch. Port 14 can be set to the input mode or output mode in 1-bit units using port mode register 14 (PM14). When the P140 to P143 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 14 (PU14). This port can also be used for segment output. Reset signal generation sets port 14 to input mode. Figure 4-14 shows a block diagram of port 14.
CHAPTER 4 PORT FUNCTIONS 4.2.9 Port 15 Port 15 is a 4-bit I/O port with an output latch. Port 15 can be set to the input mode or output mode in 1-bit units using port mode register 15 (PM15). When the P150 to P153 pins are used as an input port, use of an on-chip pull-up resistor can be specified in 1-bit units by pull-up resistor option register 15 (PU15). This port can also be used for segment output. Reset signal generation sets port 15 to input mode. Figure 4-15 shows a block diagram of port 15.
CHAPTER 4 PORT FUNCTIONS 4.3 Registers Controlling Port Function Port functions are controlled by the following seven types of registers.
CHAPTER 4 PORT FUNCTIONS Figure 4-16.
CHAPTER 4 PORT FUNCTIONS (2) Port registers (P1 to P4, P10 to P12, P14, P15) These registers write the data that is output from the chip when data is output from a port. If the data is read in the input mode, the pin level is read. If it is read in the output mode, the output latch value is read. These registers can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H.
CHAPTER 4 PORT FUNCTIONS (3) Pull-up resistor option registers (PU1, PU3, PU4, PU10 to PU12, PU14, PU15) These registers specify whether the on-chip pull-up resistors of P12, P13, P31 to P34, P40, P100, P101, P112, P113, P120, P140 to P143, or P150 to P153 are to be used or not. On-chip pull-up resistors can be used in 1-bit units only for the bits set to input mode of the pins to which the use of an on-chip pull-up resistor has been specified in PU1, PU3, PU4, PU10 to PU12, PU14, and PU15.
CHAPTER 4 PORT FUNCTIONS (4) Port function register 1 (PF1) This register sets the pin functions of P13/TxD0/KR4/ pins. PF1 is set using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PF1 to 00H. Remark The functions within arrowheads (< >) can be assigned by setting the input switch control register (ISC). Figure 4-19.
CHAPTER 4 PORT FUNCTIONS (6) Port function register ALL (PFALL) This register sets whether to use pins P10, P11, P14, and P15 as port pins (other than segment output pins) or segment output pins. PFALL is set using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PFALL to 00H. Figure 4-21.
CHAPTER 4 PORT FUNCTIONS (7) A/D port configuration register 0 (ADPC0) (μPD78F041x only) This register switches the P20/ANI0 to P25/ANI5 pins to analog input of A/D converter or digital I/O of port. ADPC0 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 08H. Caution Set the values shown in Figure 4-22 after the reset is released. Figure 4-22.
CHAPTER 4 PORT FUNCTIONS 4.4 Port Function Operations Port operations differ depending on whether the input or output mode is set, as shown below. Caution In the case of 1-bit memory manipulation instruction, although a single bit is manipulated, the port is accessed as an 8-bit unit. Therefore, on a port with a mixture of input and output pins, the output latch contents for pins specified as input are undefined, even for bits other than the manipulated bit. 4.4.
CHAPTER 4 PORT FUNCTIONS 4.5 Settings of PFALL, PF2, PF1, ISC, Port Mode Register, and Output Latch When Using Alternate Function To use the alternate function of a port pin, set the port mode register and output latch as shown in Table 4-5. Table 4-5.
CHAPTER 4 PORT FUNCTIONS Table 4-5.
CHAPTER 4 PORT FUNCTIONS Notes 1. 2. μPD78F041x only. The functions of the P20/ANI0 to P25/ANI5 pins are determined according to the settings of port function register 2 (PF2), A/D port configuration register 0 (ADPC0), port mode register 2 (PM2), analog input channel specification register (ADS). Note Table 4-6.
CHAPTER 5 CLOCK GENERATOR 5.1 Functions of Clock Generator The clock generator generates the clock to be supplied to the CPU and peripheral hardware. The following three kinds of system clocks and clock oscillators are selectable. (1) Main system clock <1> X1 oscillator This circuit oscillates a clock of fX = 2 to 10 MHz by connecting a resonator to X1 and X2. Oscillation can be stopped by executing the STOP instruction or using the main OSC control register (MOC).
CHAPTER 5 CLOCK GENERATOR (3) Internal low-speed oscillation clock (clock for watchdog timer) • Internal low-speed oscillator This circuit oscillates a clock of fRL = 240 kHz (TYP.). After a reset release, the internal low-speed oscillation clock always starts operating. Oscillation can be stopped by using the internal oscillation mode register (RCM) when “internal low-speed oscillator can be stopped by software” is set by option byte.
108 Figure 5-1.
CHAPTER 5 CLOCK GENERATOR Remarks 1. fX: 2. fRH: X1 clock oscillation frequency Internal high-speed oscillation clock frequency 3. fEXCLK: External main system clock frequency 4. fXH: High-speed system clock frequency 5. fXP: Main system clock frequency 6. fPRS: Peripheral hardware clock frequency 7. fCPU: CPU clock frequency 8. fXT: XT1 clock oscillation frequency 9. fSUB: Subsystem clock frequency 10. fRL: Internal low-speed oscillation clock frequency 5.
CHAPTER 5 CLOCK GENERATOR Figure 5-2.
CHAPTER 5 CLOCK GENERATOR (2) Processor clock control register (PCC) This register is used to select the CPU clock, the division ratio, and operation mode for subsystem clock. PCC is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PCC to 01H. Figure 5-3.
CHAPTER 5 CLOCK GENERATOR Table 5-2. Relationship Between CPU Clock and Minimum Instruction Execution Time CPU Clock (fCPU) Minimum Instruction Execution Time: 2/fCPU Main System Clock High-Speed System Clock Note Subsystem Clock Internal High-Speed Note Oscillation Clock At 10 MHz Operation At 8 MHz (TYP.) Operation At 32.768 kHz Operation fXP 0.2 μs 0.25 μs (TYP.) − fXP/2 0.4 μs 0.5 μs (TYP.) − fXP/2 2 0.8 μs 1.0 μs (TYP.) − fXP/2 3 1.6 μs 2.0 μs (TYP.) − fXP/2 4 3.2 μs 4.
CHAPTER 5 CLOCK GENERATOR (4) Internal oscillation mode register (RCM) This register sets the operation mode of internal oscillator. RCM can be set by a 1-bit or 8-bit memory manipulation instruction. Note 1 Reset signal generation sets this register to 80H . Figure 5-4.
CHAPTER 5 CLOCK GENERATOR (5) Main OSC control register (MOC) This register selects the operation mode of the high-speed system clock. This register is used to stop the X1 oscillator or to disable an external clock input from the EXCLK pin when the CPU operates with a clock other than the high-speed system clock. MOC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 80H. Figure 5-5.
CHAPTER 5 CLOCK GENERATOR (6) Main clock mode register (MCM) This register selects the main system clock supplied to CPU clock and clock supplied to peripheral hardware clock. MCM can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 5-6.
CHAPTER 5 CLOCK GENERATOR (7) Oscillation stabilization time counter status register (OSTC) This is the register that indicates the count status of the X1 clock oscillation stabilization time counter. When X1 clock oscillation starts with the internal high-speed oscillation clock or subsystem clock used as the CPU clock, the X1 clock oscillation stabilization time can be checked. OSTC can be read by a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 5 CLOCK GENERATOR (8) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released.
CHAPTER 5 CLOCK GENERATOR (9) Internal high-speed oscillation trimming register (HIOTRM) This register corrects the accuracy of the internal high-speed oscillator. The accuracy can be corrected by selfmeasuring the frequency of the internal high-speed oscillator, using a subsystem clock using a crystal resonator or using a timer with high-accuracy external clock input, such as a real-time counter. HIOTRM can be set by an 8-bit memory manipulation instruction. Reset signal generation sets HIOTRM to 10H.
CHAPTER 5 CLOCK GENERATOR Figure 5-9. Format of Internal High-speed Oscillation Trimming Register (HIOTRM) Address: FF30H After reset: 10H R/W Symbol 7 6 5 4 3 2 1 0 HIOTRM 0 0 0 TTRM4 TTRM3 TTRM2 TTRM1 TTRM0 TTRM4 TTRM3 TTRM2 TTRM1 TTRM0 Clock correction value (Target) (2.7 V ≤ VDD ≤ 5.5 V) MIN. TYP. MAX. 0 0 0 0 0 TBD −4.88% TBD 0 0 0 0 1 TBD −4.62% TBD 0 0 0 1 0 TBD −4.33% TBD 0 0 0 1 1 TBD −4.03% TBD 0 0 1 0 0 TBD −3.
CHAPTER 5 CLOCK GENERATOR 5.4 System Clock Oscillator 5.4.1 X1 oscillator The X1 oscillator oscillates with a crystal resonator or ceramic resonator (2 to 10 MHz) connected to the X1 and X2 pins. An external clock can also be input. In this case, input the clock signal to the EXCLK pin. Figure 5-10 shows an example of the external circuit of the X1 oscillator. Figure 5-10.
CHAPTER 5 CLOCK GENERATOR Figure 5-12 shows examples of incorrect resonator connection. Figure 5-12. Examples of Incorrect Resonator Connection (1/2) (a) Too long wiring (b) Crossed signal line PORT VSS Remark X1 X2 VSS X1 X2 When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side.
CHAPTER 5 CLOCK GENERATOR Figure 5-12. Examples of Incorrect Resonator Connection (2/2) (c) Wiring near high alternating current (d) Current flowing through ground line of oscillator (potential at points A, B, and C fluctuates) VDD Pmn X1 X2 VSS High current VSS A X1 B X2 C High current (e) Signals are fetched VSS Remark X1 X2 When using the subsystem clock, replace X1 and X2 with XT1 and XT2, respectively. Also, insert resistors in series on the XT2 side. Caution 2.
CHAPTER 5 CLOCK GENERATOR 5.4.3 When subsystem clock is not used If it is not necessary to use the subsystem clock for low power consumption operations, or if not using the subsystem clock as an I/O port, set the XT1 and XT2 pins to Input port mode (OSCSELS = 0) and independently connect to VDD or VSS via a resistor. Remark OSCSELS: Bit 4 of clock operation mode select register (OSCCTL) 5.4.4 Internal high-speed oscillator The internal high-speed oscillator is incorporated in the 78K0/LC3.
CHAPTER 5 CLOCK GENERATOR 5.5 Clock Generator Operation The clock generator generates the following clocks and controls the operation modes of the CPU, such as standby mode (see Figure 5-1).
CHAPTER 5 CLOCK GENERATOR Figure 5-13. Clock Generator Operation When Power Supply Voltage Is Turned On (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) Power supply voltage (VDD) 1.8 V 1.59 V (TYP.) 0.5 V/ms (MIN.) 0V Internal reset signal <1> CPU clock <3> Waiting for voltage stabilization (1.93 to 5.
CHAPTER 5 CLOCK GENERATOR Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via software settings. The internal high-speed oscillation clock and high-speed system clock can be stopped by executing the STOP instruction (see (4) in 5.6.1 Example of controlling high-speed system clock, (3) in 5.6.2 Example of controlling internal high-speed oscillation clock, and (4) in 5.6.3 Example of controlling subsystem clock). Figure 5-14.
CHAPTER 5 CLOCK GENERATOR Remark While the microcontroller is operating, a clock that is not used as the CPU clock can be stopped via software settings. The internal high-speed oscillation clock and high-speed system clock can be stopped by executing the STOP instruction (see (4) in 5.6.1 Example of controlling high-speed system clock, (3) in 5.6.2 Example of controlling internal high-speed oscillation clock, and (4) in 5.6.3 Example of controlling subsystem clock). 5.6 Controlling Clock 5.6.
CHAPTER 5 CLOCK GENERATOR (2) Example of setting procedure when using the external main system clock <1> Setting P121/X1 and P122/X2/EXCLK pins and selecting operation mode (OSCCTL register) When EXCLK and OSCSEL are set to 1, the mode is switched from port mode to external clock input mode.
CHAPTER 5 CLOCK GENERATOR (4) Example of setting procedure when stopping the high-speed system clock The high-speed system clock can be stopped in the following two ways.
CHAPTER 5 CLOCK GENERATOR (1) Example of setting procedure when restarting oscillation of the internal high-speed oscillation clockNote 1 <1> Setting restart of oscillation of the internal high-speed oscillation clock (RCM register) When RSTOP is cleared to 0, the internal high-speed oscillation clock starts operating. <2> Waiting for the oscillation accuracy stabilization time of internal high-speed oscillation clock (RCM register) Wait until RSTS is set to 1Note 2. Notes 1.
CHAPTER 5 CLOCK GENERATOR (3) Example of setting procedure when stopping the internal high-speed oscillation clock The internal high-speed oscillation clock can be stopped in the following two ways.
CHAPTER 5 CLOCK GENERATOR (1) Example of setting procedure when oscillating the XT1 clock <1> Setting XT1 and XT2 pins and selecting operation mode (PCC and OSCCTL registers) When OSCSELS is set as any of the following, the mode is switched from port mode to XT1 oscillation mode.
CHAPTER 5 CLOCK GENERATOR 5.6.4 Example of controlling internal low-speed oscillation clock The internal low-speed oscillation clock cannot be used as the CPU clock. Only the following peripheral hardware can operate with this clock. • Watchdog timer 7 9 • 8-bit timer H1 (if fRL, fRL/2 or fRL/2 is selected as the count clock) 3 • LCD controller/driver (if fRL/2 is selected as the LCD source clock) In addition, the following operation modes can be selected by the option byte.
CHAPTER 5 CLOCK GENERATOR 5.6.6 CPU clock status transition diagram Figure 5-15 shows the CPU clock status transition diagram of this product. Figure 5-15. CPU Clock Status Transition Diagram (When 1.59 V POC Mode Is Set (Option Byte: POCMODE = 0)) Internal low-speed oscillation: Woken up Internal high-speed oscillation: Woken up X1 oscillation/EXCLK input: Stops (I/O port mode) XT1 oscillation input: Stops (Input port mode) Power ON VDD < 1.59 V (TYP.) (A) VDD ≥ 1.59 V (TYP.
CHAPTER 5 CLOCK GENERATOR Table 5-5 shows transition of the CPU clock and examples of setting the SFR registers. Table 5-5. CPU Clock Transition and SFR Register Setting Examples (1/4) (1) CPU operating with internal high-speed oscillation clock (B) after reset release (A) Status Transition SFR Register Setting (A) → (B) SFR registers do not have to be set (default status after reset release).
CHAPTER 5 CLOCK GENERATOR Table 5-5.
CHAPTER 5 CLOCK GENERATOR Table 5-5. CPU Clock Transition and SFR Register Setting Examples (3/4) (6) CPU clock changing from high-speed system clock (C) to internal high-speed oscillation clock (B) (Setting sequence of SFR registers) Setting Flag of SFR Register RSTOP RSTS MCM0 0 Confirm this flag is 1.
CHAPTER 5 CLOCK GENERATOR Table 5-5.
CHAPTER 5 CLOCK GENERATOR 5.6.7 Condition before changing CPU clock and processing after changing CPU clock Condition before changing the CPU clock and processing after changing the CPU clock are shown below. Table 5-6.
CHAPTER 5 CLOCK GENERATOR 5.6.8 Time required for switchover of CPU clock and main system clock By setting bits 0 to 2 (PCC0 to PCC2) and bit 4 (CSS) of the processor clock control register (PCC), the CPU clock can be switched (between the main system clock and the subsystem clock) and the division ratio of the main system clock can be changed.
CHAPTER 5 CLOCK GENERATOR Table 5-8. Maximum Time Required for Main System Clock Switchover Set Value Before Switchover Set Value After Switchover MCM0 MCM0 0 0 1 1 + 2fRH/fXH clock 1 1 + 2fXH/fRH clock Caution When switching the internal high-speed oscillation clock to the high-speed system clock, bit 2 (XSEL) of MCM must be set to 1 in advance. The value of XSEL can be changed only once after a reset release. Remarks 1.
CHAPTER 5 CLOCK GENERATOR 5.6.10 Peripheral hardware and source clocks The following lists peripheral hardware and source clocks incorporated in the 78K0/LC3. Table 5-10.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.1 Functions of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 has the following functions. (1) Interval timer 16-bit timer/event counter 00 generates an interrupt request at the preset time interval. (2) Square-wave output 16-bit timer/event counter 00 can output a square wave with any selected frequency. (3) External event counter 16-bit timer/event counter 00 can measure the number of pulses of an externally input signal.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.2 Configuration of 16-Bit Timer/Event Counter 00 16-bit timer/event counter 00 includes the following hardware. Table 6-1.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Cautions 2. If clearing of bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) to 00 and input of the capture trigger conflict, then the captured data is undefined. 3. To change the mode from the capture mode to the comparison mode, first clear the TMC003 and TMC002 bits to 00, and then change the setting. A value that has been once captured remains stored in CR000 unless the device is reset.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-3. Format of 16-Bit Timer Capture/Compare Register 000 (CR000) Address: FF12H, FF13H After reset: 0000H R/W FF13H 15 14 13 12 FF12H 11 10 9 8 7 6 5 4 3 2 1 0 CR000 (i) When CR000 is used as a compare register The value set in CR000 is constantly compared with the TM00 count value, and an interrupt request signal (INTTM000) is generated if they match. The value is held until CR000 is rewritten.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 (iii) Setting range when CR000 or CR010 is used as a compare register When CR000 or CR010 is used as a compare register, set it as shown below. Operation CR000 Register Setting Range 0000H < N ≤ FFFFH Operation as interval timer CR010 Register Setting Range 0000H Note ≤ M ≤ FFFFH Normally, this setting is not used. Mask the Operation as square-wave output match interrupt signal (INTTM010).
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Table 6-2.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 6.3 Registers Controlling 16-Bit Timer/Event Counter 00 Registers used to control 16-bit timer/event counter 00 are shown below.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-5. Format of 16-Bit Timer Mode Control Register 00 (TMC00) Address: FFBAH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 <0> TMC00 0 0 0 0 TMC003 TMC002 TMC001 OVF00 TMC003 TMC002 0 0 Operation enable of 16-bit timer/event counter 00 Disables 16-bit timer/event counter 00 operation. Stops supplying operating clock. Clears 16-bit timer counter 00 (TM00).
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 (2) Capture/compare control register 00 (CRC00) CRC00 is the register that controls the operation of CR000 and CR010. Changing the value of CRC00 is prohibited during operation (when TMC003 and TMC002 = other than 00). CRC00 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears CRC00 to 00H. Figure 6-6.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-7. Example of CR010 Capture Operation (When Rising Edge Is Specified) Valid edge Count clock TM00 N−3 N−2 N−1 N N+1 TI000 Rising edge detection CR010 N INTTM010 (3) 16-bit timer output control register 00 (TOC00) TOC00 is an 8-bit register that controls TO00 output. TOC00 can be rewritten while only OSPT00 is operating (when TMC003 and TMC002 = other than 00). Rewriting the other bits is prohibited during operation.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-8. Format of 16-Bit Timer Output Control Register 00 (TOC00) Address: FFBDH After reset: 00H R/W Symbol 7 <6> <5> 4 <3> <2> 1 <0> TOC00 0 OSPT00 OSPE00 TOC004 LVS00 LVR00 TOC001 TOE00 OSPT00 One-shot pulse output trigger via software − 0 1 One-shot pulse output The value of this bit is always “0” when it is read. Do not set this bit to 1 in a mode other than the oneshot pulse output mode.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (4) Prescaler mode register 00 (PRM00) PRM00 is the register that sets the TM00 count clock and TI000 and TI010 pin input valid edges. Rewriting PRM00 is prohibited during operation (when TMC003 and TMC002 = other than 00). PRM00 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PRM00 to 00H. Cautions 1.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-9.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (5) Input switch control register (ISC) The input source to TI000 becomes the input signal from the P33/TI000 pin, by setting ISC1 to 0. ISC can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets ISC to 00H. Figure 6-10.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 (6) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P34/TI52/TI010/TO00/RTC1HZ/INTP1 pin for timer output, set PM34 and the output latches of P34 to 0. When using the P33/TI000/RTCDIV/RTCCL/BUZ/INTP2 and P34/TI52/TI010/TO00/RTC1HZ/INTP1 pins for timer input, set PM33 and PM34 to 1. At this time, the output latches of P33 and P34 may be 0 or 1. PM3 can be set by a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4 Operation of 16-Bit Timer/Event Counter 00 6.4.1 Interval timer operation If bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control register (TMC00) are set to 11 (clear & start mode entered upon a match between TM00 and CR000), the count operation is started in synchronization with the count clock. When the value of TM00 later matches the value of CR000, TM00 is cleared to 0000H and a match interrupt signal (INTTM000) is generated.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-14. Example of Register Settings for Interval Timer Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 1 1 OVF00 0 0 Clears and starts on match between TM00 and CR000.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-15. Example of Software Processing for Interval Timer Function N N N TM00 register 0000H Operable bits (TMC003, TMC002) 00 11 CR000 register N INTTM000 signal <1> <2> <1> Count operation start flow START Register initial setting PRM00 register, CRC00 register, CR000 register, port setting TMC003, TMC002 bits = 11 Initial setting of these registers is performed before setting the TMC003 and TMC002 bits to 11.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 6.4.2 Square wave output operation When 16-bit timer/event counter 00 operates as an interval timer (see 6.4.1), a square wave can be output from the TO00 pin by setting the 16-bit timer output control register 00 (TOC00) to 03H. When TMC003 and TMC002 are set to 11 (count clear & start mode entered upon a match between TM00 and CR000), the counting operation is started in synchronization with the count clock.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-18. Example of Register Settings for Square Wave Output Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 1 1 OVF00 0 0 Clears and starts on match between TM00 and CR000.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-19.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.3 External event counter operation When bits 1 and 0 (PRM001 and PRM000) of the prescaler mode register 00 (PRM00) are set to 11 (for counting up with the valid edge of the TI000 pin) and bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 11, the valid edge of an external event input is counted, and a match interrupt signal indicating matching between TM00 and CR000 (INTTM000) is generated.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-21. Example of Register Settings in External Event Counter Mode (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 1 1 OVF00 0 0 Clears and starts on match between TM00 and CR000.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-21. Example of Register Settings in External Event Counter Mode (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) If M is set to CR000, the interrupt signal (INTTM000) is generated when the number of external events reaches (M + 1). Setting CR000 to 0000H is prohibited.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-22.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.4 Operation in clear & start mode entered by TI000 pin valid edge input When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 10 (clear & start mode entered by the TI000 pin valid edge input) and the count clock (set by PRM00) is supplied to the timer/event counter, TM00 starts counting up.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-24.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Operation in clear & start mode entered by TI000 pin valid edge input (CR000: compare register, CR010: capture register) Figure 6-25.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-26.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Operation in clear & start mode by entered TI000 pin valid edge input (CR000: capture register, CR010: compare register) Figure 6-27.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-28.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-28.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 (4) Operation in clear & start mode entered by TI000 pin valid edge input (CR000: capture register, CR010: capture register) Figure 6-29.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-30.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-30.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-31. Example of Register Settings in Clear & Start Mode Entered by TI000 Pin Valid Edge Input (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 1 0 OVF00 0/1 0 0: Inverts TO00 output on match between CR000 and CR010. 1: Inverts TO00 output on match between CR000 and CR010 and valid edge of TI000 pin. Clears and starts at valid edge input of TI000 pin.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-31.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-32.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 6.4.5 Free-running timer operation When bits 3 and 2 (TMC003 and TMC002) of 16-bit timer mode control register 00 (TMC00) are set to 01 (freerunning timer mode), 16-bit timer/event counter 00 continues counting up in synchronization with the count clock. When it has counted up to FFFFH, the overflow flag (OVF00) is set to 1 at the next clock, and TM00 is cleared (to 0000H) and continues counting. Clear OVF00 to 0 by executing the CLR instruction via software.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-34.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-36.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (3) Free-running timer mode operation (CR000: capture register, CR010: capture register) Figure 6-37.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-38.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-38.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-39. Example of Register Settings in Free-Running Timer Mode (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 0 1 OVF00 0/1 0 0: Inverts TO00 output on match between TM00 and CR000/CR010. 1: Inverts TO00 output on match between TM00 and CR000/CR010 and valid edge of TI000 pin.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-39.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-40.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.6 PPG output operation A square wave having a pulse width set in advance by CR010 is output from the TO00 pin as a PPG (Programmable Pulse Generator) signal during a cycle set by CR000 when bits 3 and 2 (TMC003 and TMC002) of 16bit timer mode control register 00 (TMC00) are set to 11 (clear & start upon a match between TM00 and CR000). The pulse cycle and duty factor of the pulse generated as the PPG output are as follows.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-42. Example of Register Settings for PPG Output Operation (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 1 1 OVF00 0 0 Clears and starts on match between TM00 and CR000.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-43.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 6.4.7 One-shot pulse output operation A one-shot pulse can be output by setting bits 3 and 2 (TMC003 and TMC002) of the 16-bit timer mode control register 00 (TMC00) to 01 (free-running timer mode) or to 10 (clear & start mode entered by the TI000 pin valid edge) and setting bit 5 (OSPE00) of 16-bit timer output control register 00 (TOC00) to 1.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-45. Example of Register Settings for One-Shot Pulse Output Operation (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 0/1 0/1 OVF00 0 0 01: Free running timer mode 10: Clear and start mode by valid edge of TI000 pin.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-45. Example of Register Settings for One-Shot Pulse Output Operation (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) This register is used as a compare register when a one-shot pulse is output. When the value of TM00 matches that of CR000, an interrupt signal (INTTM000) is generated and the TO00 output level is inverted.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-46.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-46. Example of Software Processing for One-Shot Pulse Output Operation (2/2) <1> Count operation start flow START Register initial setting PRM00 register, CRC00 register, TOC00 registerNote, CR000, CR010 registers, port setting TMC003, TMC002 bits = 01 or 10 Initial setting of these registers is performed before setting the TMC003 and TMC002 bits. Starts count operation <2> One-shot trigger input flow TOC00.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.8 Pulse width measurement operation TM00 can be used to measure the pulse width of the signal input to the TI000 and TI010 pins. Measurement can be accomplished by operating the 16-bit timer/event counter 00 in the free-running timer mode or by restarting the timer in synchronization with the signal input to the TI000 pin. When an interrupt is generated, read the value of the valid capture register and measure the pulse width.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 A pulse width can be measured in the following three ways.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (2) Measuring the pulse width by using one input signal of the TI000 pin (free-running mode) Set the free-running timer mode (TMC003 and TMC002 = 01). The count value of TM00 is captured to CR000 in the phase reverse to the valid edge detected on the TI000 pin. When the valid edge of the TI000 pin is detected, the count value of TM00 is captured to CR010.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 (3) Measuring the pulse width by using one input signal of the TI000 pin (clear & start mode entered by the TI000 pin valid edge input) Set the clear & start mode entered by the TI000 pin valid edge (TMC003 and TMC002 = 10). The count value of TM00 is captured to CR000 in the phase reverse to the valid edge of the TI000 pin, and the count value of TM00 is captured to CR010 and TM00 is cleared (0000H) when the valid edge of the TI000 pin is detected.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-52. Example of Register Settings for Pulse Width Measurement (1/2) (a) 16-bit timer mode control register 00 (TMC00) TMC003 TMC002 TMC001 0 0 0 0 0/1 0/1 OVF00 0 0 01: Free running timer mode 10: Clear and start mode entered by valid edge of TI000 pin. (b) Capture/compare control register 00 (CRC00) CRC002 CRC001 CRC000 0 0 0 0 0 1 0/1 1 1: CR000 used as capture register 0: TI010 pin is used as capture trigger of CR000.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-52. Example of Register Settings for Pulse Width Measurement (2/2) (e) 16-bit timer counter 00 (TM00) By reading TM00, the count value can be read. (f) 16-bit capture/compare register 000 (CR000) This register is used as a capture register. Either the TI000 or TI010 pin is selected as a capture trigger. When a specified edge of the capture trigger is detected, the count value of TM00 is stored in CR000.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-53.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-53. Example of Software Processing for Pulse Width Measurement (2/2) <1> Count operation start flow START Register initial setting PRM00 register, CRC00 register, port setting TMC003, TMC002 bits = 01 or 10 Initial setting of these registers is performed before setting the TMC003 and TMC002 bits.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.4.9 External 24-bit event counter operation 16-bit timer/event counter 00 can be operated to function as an external 24-bit event counter, by connecting 16-bit timer/event counter 00 and 8-bit timer/event counter 52 in cascade, and using the external event counter function of 8bit timer/event counter 52.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 Figure 6-54.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Setting <1> Each mode of TM00 and TM52 is set. (a) Set TM00 as an interval timer. Select TM52 output as the count clock. - TMC00: Set to operation prohibited. (TMC00 = 00000000B) - CRC00: Set to operation as a compare register. - TOC00: Setting TO00 pin output is prohibited upon a match between CR000 and TM00 - PRM00: TM52 output selected as a count clock.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 <3> When the TM52 and CR52 (= FFH) values match, TM52 is cleared to 00, and the match signal causes TM000 to start counting up. Then, when the TM000 and CR000 values match, TM00 is cleared to 0000H, and a match interrupt signal (INTTM000) is generated.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 Figure 6-56. Operation Flowchart of External 24-bit Event Counter Set TMH2 to PWM mode Note Set TM52 to external event counter Set TM00 to interval timer Starts TM00 count operation Set in this order Starts TM52 count operation Starts TMH2 count operation Note Generates INTTMH2? Read TM00 counter value Read TM52 counter value TMC003 = 0, TMC002 = 0 TCE52 = 0 These operations must be restarted since the counter is cleared when timer operation is stopped.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 (2) Cautions for input enable control for TI52 pin The input enable control signal (TMH2 output signal) for the TI52 pin is synchronized by the TI52 pin input clock, as described in Figure 6-54 Configuration Diagram of External 24-bit Event Counter and Figure 6-55 Operation Timing of External 24-bit Event Counter. Thus, when the counter is operated as an external event counter, an error up to one count may be caused.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.5 Special Use of TM00 6.5.1 Rewriting CR010 during TM00 operation In principle, rewriting CR000 and CR010 of the 78K0/LC3 when they are used as compare registers is prohibited while TM00 is operating (TMC003 and TMC002 = other than 00).
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 (2) Setting LVS00 and LVR00 Set LVS00 and LVR00 using the following procedure. Figure 6-57. Example of Flow for Setting LVS00 and LVR00 Bits Setting TOC00.OSPE00, TOC004, TOC001 bits <1> Setting of timer output operation Setting TOC00.TOE00 bit Setting TOC00.LVS00, LVR00 bits Setting TMC00.TMC003, TMC002 bits <2> Setting of timer output F/F <3> Enabling timer operation Caution Be sure to set LVS00 and LVR00 following steps <1>, <2>, and <3> above.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 6.6 Cautions for 16-Bit Timer/Event Counter 00 (1) Restrictions for each channel of 16-bit timer/event counter 00 Table 6-3 shows the restrictions for each channel. Table 6-3.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 (4) Timing of holding data by capture register (a) When the valid edge is input to the TI000/TI010 pin and the reverse phase of the TI000 pin is detected while CR000/CR010 is read, CR010 performs a capture operation but the read value of CR000/CR010 is not guaranteed.
CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00 (7) Operation of OVF00 flag (a) Setting OVF00 flag (1) The OVF00 flag is set to 1 in the following case, as well as when TM00 overflows. Select the clear & start mode entered upon a match between TM00 and CR000. ↓ Set CR000 to FFFFH. ↓ When TM00 matches CR000 and TM00 is cleared from FFFFH to 0000H Figure 6-61.
CHAPTER 6 16-BIT TIMER/EVENT COUNTERS 00 (9) Capture operation (a) When valid edge of TI000 is specified as count clock When the valid edge of TI000 is specified as the count clock, the capture register for which TI000 is specified as a trigger does not operate correctly.
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52 7.1 Functions of 8-Bit Timer/Event Counters 50, 51, and 52 8-bit timer/event counters 50, 51 and 52 have the following functions. • Interval timer Note • External event counter Note TM52 only. TM52 and TM00 can be connected in cascade to be used as an external 24-bit event counter. Also, the external event input of TM52 can be input enable-controlled via TMH2. For detail, see CHAPTER 6 16-BIT TIMER/EVENT COUNTER 00. 7.
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52 Figure 7-1. Block Diagram of 8-Bit Timer/Event Counter 50 8-bit timer compare register 50 (CR50) Match Selector fPRS fPRS/2 fPRS/22 fPRS/26 fPRS/28 fPRS/213 Mask circuit Internal bus INTTM50 S Q INV 8-bit timer counter 50 (TM50) To TMH0 To UART0 To UART6 R 3 Clear TCE50 LVS50 LVR50 TMC501 TCL502 TCL501 TCL500 8-bit timer mode control register 50 (TMC50) Timer clock selection register 50 (TCL50) Internal bus Figure 7-2.
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52 Figure 7-3.
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52 (1) 8-bit timer counter 5n (TM5n) TM5n is an 8-bit register that counts the count pulses and is read-only. The counter is incremented in synchronization with the rising edge of the count clock. Figure 7-4. Format of 8-Bit Timer Counter 5n (TM5n) Address: FF16H (TM50), FF6FH (TM51), FF51H (TM52) After reset: 00H R Symbol TM5n (n = 0-2) In the following situations, the count value is cleared to 00H.
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52 7.3 Registers Controlling 8-Bit Timer/Event Counters 50, 51, and 52 The following five registers are used to control 8-bit timer/event counters 50, 51, and 52.
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52 Figure 7-7. Format of Timer Clock Selection Register 51 (TCL51) Address: FF8CH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 TCL51 0 0 0 0 0 TCL512 TCL511 TCL510 TCL512 TCL511 TCL510 0 0 0 0 1 0 1 0 fPRS 0 1 1 fPRS/2 1 0 0 0 1 fPRS = fPRS = fPRS = 2 MHz 5 MHz 10 MHz Setting prohibited 0 1 Notes 1. Note1 Count clock selection Note2 2 MHz 5 MHz 10 MHz 1 MHz 2.5 MHz 5 MHz fPRS/2 4 125 kHz 312.
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52 Figure 7-8. Format of Timer Clock Selection Register 52 (TCL52) Address: FF5BH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 TCL52 0 0 0 0 0 TCL522 TCL521 TCL520 TCL522 TCL521 TCL520 fPRS = fPRS = fPRS = 2 MHz 5 MHz 10 MHz 0 0 0 Falling edge of clock selected by ISC2 0 0 1 Rising edge of clock selected by ISC2 0 1 0 fPRS 0 1 1 fPRS/2 1 1 1 1 Notes 1.
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52 (2) 8-bit timer mode control register 5n (TMC5n) TMC5n is a register that controls the count operation of 8-bit timer counter 5n (TM5n). TMC5n can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Remark n = 0 to 2 Figure 7-9.
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52 Figure 7-10. Format of 8-Bit Timer Mode Control Register 51 (TMC51) Address: FF43H After reset: 00H R/W Note Symbol <7> 6 5 4 3 2 1 0 TMC51 TCE51 0 0 0 0 0 0 0 TCE51 TM51 count operation control 0 After clearing to 0, count operation disabled (counter stopped) 1 Count operation start Caution Be sure to clear bits 0 to 6 to 0. Figure 7-11.
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52 (3) Input switch control register (ISC) By setting ISC2 to 1, the TI52 input signal can be controlled via the TOH2 output signal. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 7-12.
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52 (4) Port mode registers 3 (PM3) These registers set port 3 input/output in 1-bit units. When using the P34/TI52/TI010/TO00/RTC1HZ/INTP1 pins for timer input, set PM34 to 1. The output latch of PM34 at this time may be 0 or 1. PM3 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 7-13.
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52 7.4 Operations of 8-Bit Timer/Event Counters 50, 51, and 52 7.4.1 Operation as interval timer 8-bit timer/event counter 5n operates as an interval timer that generates interrupt requests repeatedly at intervals of the count value preset to 8-bit timer compare register 5n (CR5n).
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52 Figure 7-14.
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52 7.4.2 Operation as external event counter (TM52 only) The external event counter counts the number of external clock pulses to be input to the TI52 pin by 8-bit timer counter 52 (TM52). TM52 is incremented each time the valid edge specified by timer clock selection register 52 (TCL52) is input. Either the rising or falling edge can be selected.
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52 7.5 Cautions for 8-Bit Timer/Event Counters 50, 51, and 52 (1) Timer start error An error of up to one clock may occur in the time required for a match signal to be generated after timer start. This is because 8-bit timer counters 50, 51, and 52 (TM50, TM51, and TM52) are started asynchronously to the count clock. Figure 7-16.
CHAPTER 7 8-BIT TIMER/EVENT COUNTERS 50, 51, AND 52 TM52 00H 01H 02H FFH 00H 01H FFH 00H 01H TM00 0000H 0000H 0000H 0000H 0000H 0000H 0000H 0001H 0001H TMIF52 when timer operation is started The timer does not count up upon the first overflow of TM52. The timer counts up upon second and subsequent overflows.
CHAPTER 8 8-BIT TIMERS H0, H1 AND H2 8.1 Functions of 8-Bit Timers H0, H1, and H2 8-bit timers H0, H1, and H2 have the following functions. • Interval timer • Square-wave output • PWM output Note 1 Note 2 • Carrier generator (8-bit timer H1 only) Notes 1. Note 3 TMH0 and TMH1 only. 2. However, TOH0 and TOH1 only for TOHn 3. TMH1 only. TM51 and TMH1 can be used in combination as a carrier generator mode. 8.
Figure 8-1.
236 Figure 8-2.
Figure 8-3.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 (1) 8-bit timer H compare register 0n (CMP0n) This register can be read or written by an 8-bit memory manipulation instruction. This register is used in all of the timer operation modes. This register constantly compares the value set to CMP0n with the count value of the 8-bit timer counter Hn and, when the two values match, generates an interrupt request signal (INTTMHn) and inverts the output level of TOHn.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 8.3 Registers Controlling 8-Bit Timers H0, H1, and H2 The following four registers are used to control 8-bit timers H0, H1, and H2. • 8-bit timer H mode register n (TMHMDn) • 8-bit timer H carrier control register 1 (TMCYC1)Note • Port mode register 3 (PM3) • Port register 3 (P3) Note 8-bit timer H1 only (1) 8-bit timer H mode register n (TMHMDn) This register controls the mode of timer H. This register can be set by a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 Figure 8-6.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 Cautions 1. When TMHE0 = 1, setting the other bits of TMHMD0 is prohibited. However, TMHMD0 can be refreshed (the same value is written). 2. In the PWM output mode, be sure to set the 8-bit timer H compare register 10 (CMP10) when starting the timer count operation (TMHE0 = 1) after the timer count operation was stopped (TMHE0 = 0) (be sure to set again even if setting the same value to CMP10). 3.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 Figure 8-7.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 Cautions 1. When TMHE1 = 1, setting the other bits of TMHMD1 is prohibited. However, TMHMD1 can be refreshed (the same value is written). 2. In the PWM output mode and carrier generator mode, be sure to set the 8-bit timer H compare register 11 (CMP11) when starting the timer count operation (TMHE1 = 1) after the timer count operation was stopped (TMHE1 = 0) (be sure to set again even if setting the same value to CMP11). 3.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 Figure 8-8.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 (2) 8-bit timer H carrier control register 1 (TMCYC1) This register controls the remote control output and carrier pulse output status of 8-bit timer H1. This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Figure 8-9.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 8.4 Operation of 8-Bit Timers H0, H1 and H2 8.4.1 Operation as interval timer/square-wave output When the 8-bit timer counter Hn and compare register 0n (CMP0n) match, an interrupt request signal (INTTMHn) is generated and the 8-bit timer counter Hn is cleared to 00H. Compare register 1n (CMP1n) is not used in interval timer mode.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 Figure 8-12.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 Figure 8-12.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 8.4.2 Operation as PWM output In PWM output mode, a pulse with an arbitrary duty and arbitrary cycle can be output. The 8-bit timer compare register 0n (CMP0n) controls the cycle of timer output (TOHn). Rewriting the CMP0n register during timer operation is prohibited. The 8-bit timer compare register 1n (CMP1n) controls the duty of timer output (TOHn). Rewriting the CMP1n register during timer operation is possible. The operation in PWM output mode is as follows.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 <4> When the 8-bit timer counter Hn and the CMP1n register match, an inactive level is output and the compare register to be compared with 8-bit timer counter Hn is changed from the CMP1n register to the CMP0n register. At this time, 8-bit timer counter Hn is not cleared and the INTTMHn signal is not generated. <5> By performing procedures <3> and <4> repeatedly, a pulse with an arbitrary duty can be obtained. <6> To stop the count operation, set TMHEn = 0.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 Figure 8-14. Operation Timing in PWM Output Mode (1/4) (a) Basic operation Count clock 8-bit timer counter Hn 00H 01H A5H 00H 01H 02H CMP0n A5H CMP1n 01H A5H 00H 01H 02H A5H 00H TMHEn INTTMHn TOHn (TOLEVn = 0) <1> <2> <3> <4> TOHn (TOLEVn = 1) <1> The count operation is enabled by setting the TMHEn bit to 1. Start 8-bit timer counter Hn by masking one count clock to count up. At this time, PWM output outputs an inactive level.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 Figure 8-14.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 Figure 8-14.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 Figure 8-14. Operation Timing in PWM Output Mode (4/4) (e) Operation by changing CMP1n (CMP1n = 02H → 03H, CMP0n = A5H) Count clock 8-bit timer counter Hn 00H 01H 02H 80H A5H 00H 01H 02H 03H A5H 00H 01H 02H 03H A5H 00H A5H CMP0n 02H CMP1n 02H (03H) <2> 03H <2>’ TMHEn INTTMHn TOHn (TOLEVn = 0) <1> <3> <4> <5> <6> <1> The count operation is enabled by setting TMHEn = 1. Start 8-bit timer counter Hn by masking one count clock to count up.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 8.4.3 Carrier generator operation (8-bit timer H1 only) In the carrier generator mode, the 8-bit timer H1 is used to generate the carrier signal of an infrared remote controller, and the 8-bit timer/event counter 51 is used to generate an infrared remote control signal (time count). The carrier clock generated by the 8-bit timer H1 is output in the cycle set by the 8-bit timer/event counter 51.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 To control the carrier pulse output during a count operation, the NRZ1 and NRZB1 bits of the TMCYC1 register have a master and slave bit configuration. The NRZ1 bit is read-only but the NRZB1 bit can be read and written. The INTTM51 signal is synchronized with the 8-bit timer H1 count clock and is output as the INTTM5H1 signal. The INTTM5H1 signal becomes the data transfer signal of the NRZ1 bit, and the NRZB1 bit value is transferred to the NRZ1 bit.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 Setting <1> Set each register. Figure 8-16.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 <10> By performing the procedures above, an arbitrary carrier clock is obtained. To stop the count operation, clear TMHE1 to 0. If the setting value of the CMP01 register is N, the setting value of the CMP11 register is M, and the count clock frequency is fCNT, the carrier clock output cycle and duty are as follows. • Carrier clock output cycle = (N + M + 2)/fCNT • Duty = High-level width/carrier clock output width = (M + 1)/(N + M + 2) Cautions 1.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 Figure 8-17.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 Figure 8-17.
CHAPTER 8 8-BIT TIMERS H0, H1, AND H2 Figure 8-17. Carrier Generator Mode Operation Timing (3/3) (c) Operation when CMP11 is changed 8-bit timer H1 count clock 8-bit timer counter H1 count value 00H 01H N 00H 01H M 00H N 00H 01H L 00H N CMP01 <3> M CMP11 <3>’ M (L) L TMHE1 INTTMH1 <2> Carrier clock <4> <5> <1> <1> When TMHE1 = 1 is set, the 8-bit timer H1 starts a count operation. At that time, the carrier clock remains default.
CHAPTER 9 REAL-TIME COUNTER 9.1 Functions of Real-Time Counter The real-time counter has the following features. • Having counters of year, month, week, day, hour, minute, and second, and can count up to 99 years. • Constant-period interrupt function (period: 1 month to 0.5 seconds) • Alarm interrupt function (alarm: week, hour, minute) • Interval interrupt function • Pin output function of 1 Hz • Pin output function of 512 Hz or 16.384 kHz or 32.768 kHz 9.
CHAPTER 9 REAL-TIME COUNTER Figure 9-1.
CHAPTER 9 REAL-TIME COUNTER 9.3 Registers Controlling Real-Time Counter Timer real-time counter is controlled by the following 16 registers. (1) Real-time counter clock selection register (RTCCL) This register controls the mode of real-time counter. RTCCL can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 9-2.
CHAPTER 9 REAL-TIME COUNTER Figure 9-3. Format of Real-Time Counter Control Register 0 (RTCC0) Address: FF89H After reset: 00H R/W Symbol <7> 6 <5> <4> 3 2 1 0 RTCC0 RTCE 0 RCLOE1 RCLOE0 AMPM CT2 CT1 CT0 RTCE Real-time counter operation control 0 Stops counter operation. 1 Starts counter operation. RCLOE1 RTC1HZ pin output control 0 Disables output of RTC1HZ pin (1 Hz). 1 Enables output of RTC1HZ pin (1 Hz).
CHAPTER 9 REAL-TIME COUNTER Table 9-2.
CHAPTER 9 REAL-TIME COUNTER Figure 9-4. Format of Real-Time Counter Control Register 1 (RTCC1) (2/2) RIFG Constant-period interrupt status flag 0 Constant-period interrupt is not generated. 1 Constant-period interrupt is generated. This flag indicates the status of generation of the constant-period interrupt. When the constant-period interrupt is generated, it is set to “1”. This flag is cleared when “0” is written to it. Writing “1” to it is invalid.
CHAPTER 9 REAL-TIME COUNTER (4) Real-time counter control register 2 (RTCC2) The RTCC2 register is an 8-bit register that is used to control the interval interrupt function and the RTCDIV pin. RTCC2 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 9-5.
CHAPTER 9 REAL-TIME COUNTER (5) Sub-count register (RSUBC) The RSUBC register is a 16-bit register that counts the reference time of 1 second of the real-time counter. It takes a value of 0000H to 7FFFH and counts 1 second with a clock of 32.768 kHz. RSUBC can be set by a 16-bit memory manipulation instruction. Reset signal generation clears this register to 0000H. Cautions 1. When a correction is made by using the SUBCUD register, the value may become 8000H or more. 2.
CHAPTER 9 REAL-TIME COUNTER (7) Minute count register (MIN) The MIN register is an 8-bit register that takes a value of 0 to 59 (decimal) and indicates the count value of minutes. It counts up when the second counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later. Set a decimal value of 00 to 59 to this register in BCD code.
CHAPTER 9 REAL-TIME COUNTER (9) Day count register (DAY) The DAY register is an 8-bit register that takes a value of 1 to 31 (decimal) and indicates the count value of days. It counts up when the hour counter overflows. This counter counts as follows.
CHAPTER 9 REAL-TIME COUNTER (11) Month count register (MONTH) The MONTH register is an 8-bit register that takes a value of 1 to 12 (decimal) and indicates the count value of months. It counts up when the day counter overflows. When data is written to this register, it is written to a buffer and then to the counter up to 2 clocks (32.768 kHz) later. Set a decimal value of 01 to 12 to this register in BCD code.
CHAPTER 9 REAL-TIME COUNTER (13) Watch error correction register (SUBCUD) This register is used to correct the count value of the sub-count register (RSUBC). SUBCUD can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 9-14.
CHAPTER 9 REAL-TIME COUNTER (15) Alarm hour register (ALARMWH) This register is used to set hours of alarm. ALARMWH can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 12H. Caution Set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in BCD code. If a value outside the range is set, the alarm is not detected. Figure 9-16.
CHAPTER 9 REAL-TIME COUNTER (16) Alarm week register (ALARMWW) This register is used to set date of alarm. ALARMWW can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Caution Set a decimal value of 00 to 23, 01 to 12, or 21 to 32 to this register in BCD code. If a value outside the range is set, the alarm is not detected. Figure 9-17.
CHAPTER 9 REAL-TIME COUNTER 9.4 Real-Time Counter Operation 9.4.1 Starting operation of real-time counter Figure 9-18. Procedure for Starting Operation of Real-Time Counter Start Stops counter operation. RTCE = 0 Setting AMPM, CT2 to CT0 Selects 12-/24-hour system and interrupt (INTRTC). Setting SEC (clearing RSUBC) Sets second count register. Setting MIN Sets minute count register. Setting HOUR Sets hour count register. Setting WEEK Sets week count register. Sets day count register.
CHAPTER 9 REAL-TIME COUNTER 9.4.2 Reading/writing real-time counter Read or write the counter when RWAIT = 1. Figure 9-19. Procedure for Reading Real-Time Counter Start No RWAIT = 1 Stops SEC to YEAR counters. Mode to read and write count values RWST = 1? Checks wait status of counter. Yes Reading SEC Reads second count register. Reading MIN Reads minute count register. Reading HOUR Reads hour count register. Reading WEEK Reads week count register.
CHAPTER 9 REAL-TIME COUNTER Figure 9-20. Procedure for Writing Real-Time Counter Start No RWAIT = 1 Stops SEC to YEAR counters. Mode to read and write count values RWST = 1? Checks wait status of counter. Yes Writing SEC Writes second count register. Writing MIN Writes minute count register. Writing HOUR Writes hour count register. Writing WEEK Writes week count register. Writing DAY Writing MONTH No Writes day count register. Writes month count register.
CHAPTER 9 REAL-TIME COUNTER 9.4.3 Setting alarm of real-time counter Set time of alarm when WALE = 0. Figure 9-21. Alarm Setting Procedure Start WALE = 0 Match operation of alarm is invalid. WALIE = 1 Interrupt is generated when alarm matches. Setting ALARMWM Sets alarm minute register. Setting ALARMWH Sets alarm hour register. Setting ALARMWW Sets alarm week register. WALE = 1 No Match operation of alarm is valid.
CHAPTER 10 WATCHDOG TIMER 10.1 Functions of Watchdog Timer The watchdog timer operates on the internal low-speed oscillation clock. The watchdog timer is used to detect an inadvertent program loop. If a program loop is detected, an internal reset signal is generated. Program loop is detected in the following cases.
CHAPTER 10 WATCHDOG TIMER 10.2 Configuration of Watchdog Timer The watchdog timer includes the following hardware. Table 10-1. Configuration of Watchdog Timer Item Configuration Control register Watchdog timer enable register (WDTE) How the counter operation is controlled, overflow time, and window open period are set by the option byte. Table 10-2.
CHAPTER 10 WATCHDOG TIMER 10.3 Register Controlling Watchdog Timer The watchdog timer is controlled by the watchdog timer enable register (WDTE). (1) Watchdog timer enable register (WDTE) Writing ACH to WDTE clears the watchdog timer counter and starts counting again. This register can be set by an 8-bit memory manipulation instruction. Note Reset signal generation sets this register to 9AH or 1AH . Figure 10-2.
CHAPTER 10 WATCHDOG TIMER 10.4 Operation of Watchdog Timer 10.4.1 Controlling operation of watchdog timer 1. When the watchdog timer is used, its operation is specified by the option byte (0080H). • Enable counting operation of the watchdog timer by setting bit 4 (WDTON) of the option byte (0080H) to 1 (the counter starts operating after a reset release) (for details, see CHAPTER 23).
CHAPTER 10 WATCHDOG TIMER Cautions 4. The operation of the watchdog timer in the HALT and STOP modes differs as follows depending on the set value of bit 0 (LSROSC) of the option byte. In HALT mode LSROSC = 0 (Internal Low-Speed LSROSC = 1 (Internal Low-Speed Oscillator Can Be Stopped by Software) Oscillator Cannot Be Stopped) Watchdog timer operation stops. Watchdog timer operation continues. In STOP mode If LSROSC = 0, the watchdog timer resumes counting after the HALT or STOP mode is released.
CHAPTER 10 WATCHDOG TIMER 10.4.3 Setting window open period of watchdog timer Set the window open period of the watchdog timer by using bits 6 and 5 (WINDOW1, WINDOW0) of the option byte (0080H). The outline of the window is as follows. • If “ACH” is written to WDTE during the window open period, the watchdog timer is cleared and starts counting again. • Even if “ACH” is written to WDTE during the window close period, an abnormality is detected and an internal reset signal is generated.
CHAPTER 10 WATCHDOG TIMER Remark If the overflow time is set to 210/fRL, the window close time and open time are as follows. Setting of Window Open Period 25% 50% 75% 100% Window close time 0 to 3.56 ms 0 to 2.37 ms 0 to 0.119 ms None Window open time 3.56 to 3.88 ms 2.37 to 3.88 ms 0.119 to 3.88 ms 0 to 3.88 ms • Overflow time: 210/fRL (MAX.) = 210/264 kHz (MAX.) = 3.88 ms • Window close time: 0 to 210/fRL (MIN.) × (1 − 0.25) = 0 to 210/216 kHz (MIN.) × 0.
CHAPTER 11 BUZZER OUTPUT CONTROLLER 11.1 Functions of Buzzer Output Controller The buzzer output is intended for square-wave output of buzzer frequency selected with CKS. Figure 11-1 shows the block diagram of buzzer output controller. Figure 11-1.
CHAPTER 11 BUZZER OUTPUT CONTROLLER 11.2 Configuration of Buzzer Output Controller The buzzer output controller includes the following hardware. Table 11-1. Configuration of Buzzer Output Controller Item Control registers Configuration Clock output selection register (CKS) Port mode register 3 (PM3) Port register 3 (P3) 11.3 Registers Controlling Buzzer Output Controller The following two registers are used to control the buzzer output controller.
CHAPTER 11 BUZZER OUTPUT CONTROLLER Figure 11-2. Format of Clock Output Selection Register (CKS) Address: FF40H Symbol CKS After reset: 00H R/W <7> 6 5 4 3 2 1 0 BZOE BCS1 BCS0 0 0 0 0 0 BZOE BUZ output enable/disable specification 0 Clock division circuit operation stopped. BUZ fixed to low level. 1 Clock division circuit operation enabled. BUZ output enabled. BCS1 BCS0 BUZ output clock selection fPRS = 5 MHz 0 0 1 1 0 1 0 1 fPRS = 10 MHz fPRS/2 10 4.88 kHz 9.
CHAPTER 11 BUZZER OUTPUT CONTROLLER (2) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P33/TI000/RTCDIV/RTCCL/BUZ/INTP2 pin for buzzer output, clear PM33 and the output latches of P33 to 0. PM3 is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM3 to FFH. Figure 11-3.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) 12.1 Function of 10-Bit Successive Approximation Type A/D Converter The 10-bit successive approximation type A/D converter converts an analog input signal into a digital value, and consists of up to 6 channels (ANI0 to ANI5) with a resolution of 10 bits. The A/D converter has the following function.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) 12.2 Configuration of 10-Bit Successive Approximation Type A/D Converter The 10-bit successive approximation type A/D converter includes the following hardware. (1) ANI0 to ANI5 pins These are the 6-channel analog input pins of the 10-bit successive approximation type A/D converter. They input analog signals to be converted into digital signals.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) (7) 8-bit A/D conversion result register (ADCRH) The A/D conversion result is loaded from the successive approximation register to this register each time A/D conversion is completed, and the ADCRH register stores the higher 8 bits of the A/D conversion result. Caution When data is read from ADCR and ADCRH, a wait cycle is generated.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) 12.3 Registers Used in 10-Bit Successive Approximation Type A/D Converter The A/D converter uses the following seven registers.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) Figure 12-4. Timing Chart When Comparator Is Used Comparator operation ADCE Comparator Conversion operation Conversion waiting Conversion operation Conversion stopped ADCS Note Note To stabilize the internal circuit, the time from the rising of the ADCE bit to the falling of the ADCS bit must be 1 μs or longer. Cautions 1.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) Table 12-2. A/D Conversion Time Selection (1) 2.7 V ≤ AVREF ≤ 5.5 V A/D Converter Mode Register (ADM) Conversion Time Selection FR3 FR2 FR1 FR0 LV1 LV0 1 × × × 0 0 fPRS = 2 MHz fPRS = 8 MHz Conversion Clock (fAD) fPRS = 10 MHz 352/fPRS Setting 44.0 μs 35.2 μs fPRS/16 prohibited 0 0 0 0 0 0 264/fPRS 33.0 μs 26.4 μs fPRS/12 0 0 0 1 0 0 176/fPRS 22.0 μs 17.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) Figure 12-5. A/D Converter Sampling and A/D Conversion Timing ADCS ← 1 or ADS rewrite ADCS Sampling timing INTAD Wait periodNote SAR clear Sampling Sampling Successive conversion Transfer SAR to ADCR, clear INTAD generation Conversion time Conversion time Note For details of wait period, see CHAPTER 29 CAUTIONS FOR WAIT.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) (3) 8-bit A/D conversion result register (ADCRH) This register is an 8-bit register that stores the A/D conversion result. The higher 8 bits of 10-bit resolution are stored. ADCRH can be read by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 12-7.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) (4) Analog input channel specification register (ADS) This register specifies the input channel of the analog voltage to be A/D converted. ADS can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 12-8.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) Figure 12-9.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) (6) Port mode register 2 (PM2) When using the ANI0/P20 to ANI5/P25 pins for analog input port, set PM20 to PM25 to 1. The output latches of P20 to P25 at this time may be 0 or 1. If PM20 to PM25 are set to 0, they cannot be used as analog input port pins. PM2 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Figure 12-10.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) 12.4 10-Bit Successive Approximation Type A/D Converter Operations 12.4.1 Basic operations of A/D converter <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1 to start the operation of the comparator. <2> Set channels for A/D conversion to analog input by using the A/D port configuration register (ADPC0) and set to input mode by using port mode register 2 (PM2).
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) Figure 12-11. Basic Operation of A/D Converter Conversion time Sampling time A/D converter operation Sampling A/D conversion Conversion result SAR Undefined Conversion result ADCR INTAD A/D conversion operations are performed continuously until bit 7 (ADCS) of the A/D converter mode register (ADM) is reset (0) by software.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) 12.4.2 Input voltage and conversion results The relationship between the analog input voltage input to the analog input pins (ANI0 to ANI5) and the theoretical A/D conversion result (stored in the 10-bit A/D conversion result register (ADCR)) is shown by the following expression. SAR = INT ( VAIN AVREF × 1024 + 0.5) ADCR = SAR × 64 or ( ADCR 64 − 0.5) × where, INT( ): AVREF 1024 ≤ VAIN < ( ADCR 64 + 0.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) 12.4.3 A/D converter operation mode The operation mode of the A/D converter is the select mode. One channel of analog input is selected from ANI0 to ANI5 by the analog input channel specification register (ADS) and A/D conversion is executed.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) The setting methods are described below. <1> Set bit 0 (ADCE) of the A/D converter mode register (ADM) to 1. <2> Set the channel to be used in the analog input mode by using bits 2 to 0 (ADPC02 to ADPC00) of the A/D port configuration register 0 (ADPC0) and bits 5 to 0 (PM25 to PM20) of port mode register 2 (PM2). <3> Select conversion time by using bits 6 to 1 (FR3 to FR0, LV1, and LV0) of ADM.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) 12.5 How to Read A/D Converter Characteristics Table Here, special terms unique to the A/D converter are explained. (1) Resolution This is the minimum analog input voltage that can be identified. That is, the percentage of the analog input voltage per bit of digital output is called 1LSB (Least Significant Bit). The percentage of 1LSB with respect to the full scale is expressed by %FSR (Full Scale Range).
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) (5) Full-scale error This shows the difference between the actual measurement value of the analog input voltage and the theoretical value (Full-scale − 3/2LSB) when the digital output changes from 1......110 to 1......111. (6) Integral linearity error This shows the degree to which the conversion characteristics deviate from the ideal linear relationship.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) 12.6 Cautions for 10-Bit Successive Approximation Type A/D Converter (1) Operating current in STOP mode The A/D converter stops operating in the STOP mode. At this time, the operating current can be reduced by clearing bit 7 (ADCS) and bit 0 (ADCE) of the A/D converter mode register (ADM) to 0. To restart from the standby status, clear bit 0 (ADIF) of interrupt request flag register 1L (IF1L) to 0 and start operation.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) Figure 12-20. Analog Input Pin Connection If there is a possibility that noise equal to or higher than AVREF or equal to or lower than AVSS may enter, clamp with a diode with a small VF value (0.3 V or lower). Reference voltage input AVREF ANI0 to ANI5 C = 100 to 1,000 pF AVSS VSS (5) ANI0/SEG21/P20 to ANI5/SEG16/P25 pins <1> The analog input pins (ANI0 to ANI5) are also used as I/O port pins (P20 to P25).
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) (8) Interrupt request flag (ADIF) The interrupt request flag (ADIF) is not cleared even if the analog input channel specification register (ADS) is changed. Therefore, if an analog input pin is changed during A/D conversion, the A/D conversion result and ADIF for the pre-change analog input may be set just before the ADS rewrite.
CHAPTER 12 10-BIT SUCCESSIVE APPROXIMATION TYPE A/D CONVERTER (μPD78F041x only) (11) Internal equivalent circuit The equivalent circuit of the analog input block is shown below. Figure 12-22. Internal Equivalent Circuit of ANIn Pin R1 R2 ANIn C1 C2 C3 Table 12-4. Resistance and Capacitance Values of Equivalent Circuit (Reference Values) AVREF R1 R2 C1 C2 C3 2.7 V TBD TBD TBD TBD TBD 4.5 V TBD TBD TBD TBD TBD Remarks 1.
CHAPTER 13 SERIAL INTERFACE UART0 13.1 Functions of Serial Interface UART0 Serial interface UART0 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, see 13.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode The functions of this mode are outlined below. For details, see 13.4.2 Asynchronous serial interface (UART) mode and 13.4.
CHAPTER 13 SERIAL INTERFACE UART0 13.2 Configuration of Serial Interface UART0 Serial interface UART0 includes the following hardware. Table 13-1.
Figure 13-1.
CHAPTER 13 SERIAL INTERFACE UART0 (1) Receive buffer register 0 (RXB0) This 8-bit register stores parallel data converted by receive shift register 0 (RXS0). Each time 1 byte of data has been received, new receive data is transferred to this register from receive shift register 0 (RXS0). If the data length is set to 7 bits the receive data is transferred to bits 0 to 6 of RXB0 and the MSB of RXB0 is always 0. If an overrun error (OVE0) occurs, the receive data is not transferred to RXB0.
CHAPTER 13 SERIAL INTERFACE UART0 13.3 Registers Controlling Serial Interface UART0 Serial interface UART0 is controlled by the following six registers.
CHAPTER 13 SERIAL INTERFACE UART0 Figure 13-2. Format of Asynchronous Serial Interface Operation Mode Register 0 (ASIM0) (2/2) PS01 PS00 Transmission operation 0 0 Does not output parity bit. Reception without parity 0 1 Outputs 0 parity. Reception as 0 parity 1 0 Outputs odd parity. Judges as odd parity. 1 1 Outputs even parity. Judges as even parity.
CHAPTER 13 SERIAL INTERFACE UART0 (2) Asynchronous serial interface reception error status register 0 (ASIS0) This register indicates an error status on completion of reception by serial interface UART0. It includes three error flag bits (PE0, FE0, OVE0). This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation, or clearing bit 7 (POWER0) or bit 5 (RXE0) of ASIM0 to 0 clears this register to 00H. 00H is read when this register is read.
CHAPTER 13 SERIAL INTERFACE UART0 (3) Baud rate generator control register 0 (BRGC0) This register selects the base clock of serial interface UART0 and the division value of the 5-bit counter. BRGC0 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 1FH. Figure 13-4.
CHAPTER 13 SERIAL INTERFACE UART0 Remarks 1. fXCLK0: Frequency of base clock selected by the TPS01 and TPS00 bits 2. fPRS: Peripheral hardware clock frequency 3. k: Value set by the MDL04 to MDL00 bits (k = 8, 9, 10, ..., 31) 4. ×: Don’t care (4) Port function register 1 (PF1) This register sets the pin functions of P13/TxD0/KR4/ pin. PF1 is set using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PF1 to 00H.
CHAPTER 13 SERIAL INTERFACE UART0 (5) Port mode register 1 (PM1) This register sets port 1 input/output in 1-bit units. When using the P13/TxD0/KR4/ pin for serial interface data output, clear PM13 to 0. The output latch of P13 at this time may be 0 or 1. When using the P12/RxD0/KR3/ pin for serial interface data input, set PM12 to 1. The output latch of P12 at this time may be 0 or 1. PM1 can be set by a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 13 SERIAL INTERFACE UART0 13.4 Operation of Serial Interface UART0 Serial interface UART0 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 13.4.1 Operation stop mode In this mode, serial communication cannot be executed, thus reducing the power consumption. In addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER0, TXE0, and RXE0) of ASIM0 to 0.
CHAPTER 13 SERIAL INTERFACE UART0 13.4.2 Asynchronous serial interface (UART) mode In this mode, 1-byte data is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
CHAPTER 13 SERIAL INTERFACE UART0 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 13-7 and 13-8 show the format and waveform example of the normal transmit/receive data. Figure 13-7. Format of Normal UART Transmit/Receive Data 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 Parity bit D7 Stop bit Character bits One data frame consists of the following bits. • Start bit ... 1 bit • Character bits ... 7 or 8 bits (LSB first) • Parity bit ...
CHAPTER 13 SERIAL INTERFACE UART0 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. (i) Even parity • Transmission Transmit data, including the parity bit, is controlled so that the number of bits that are “1” is even.
CHAPTER 13 SERIAL INTERFACE UART0 (c) Transmission If bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and bit 6 (TXE0) of ASIM0 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit shift register 0 (TXS0). The start bit, parity bit, and stop bit are automatically appended to the data.
CHAPTER 13 SERIAL INTERFACE UART0 (d) Reception Reception is enabled and the RXD0 pin input is sampled when bit 7 (POWER0) of asynchronous serial interface operation mode register 0 (ASIM0) is set to 1 and then bit 5 (RXE0) of ASIM0 is set to 1. The 5-bit counter of the baud rate generator starts counting when the falling edge of the RXD0 pin input is detected. When the set value of baud rate generator control register 0 (BRGC0) has been counted, the RXD0 pin input is sampled again ( in Figure 13-10).
CHAPTER 13 SERIAL INTERFACE UART0 (e) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 0 (ASIS0) is set as a result of data reception, a reception error interrupt (INTSR0) is generated. Which error has occurred during reception can be identified by reading the contents of ASIS0 in the reception error interrupt (INTSR0) servicing (see Figure 13-3).
CHAPTER 13 SERIAL INTERFACE UART0 13.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and a 5-bit programmable counter, and generates a serial clock for transmission/reception of UART0. Separate 5-bit counters are provided for transmission and reception.
CHAPTER 13 SERIAL INTERFACE UART0 (2) Generation of serial clock A serial clock to be generated can be specified by using baud rate generator control register 0 (BRGC0). Select the clock to be input to the 5-bit counter by using bits 7 and 6 (TPS01 and TPS00) of BRGC0. Bits 4 to 0 (MDL04 to MDL00) of BRGC0 can be used to select the division value (fXCLK0/8 to fXCLK0/31) of the 5-bit counter. 13.4.
CHAPTER 13 SERIAL INTERFACE UART0 Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception. Example: Frequency of base clock = 2.5 MHz = 2,500,000 Hz Set value of MDL04 to MDL00 bits of BRGC0 register = 10000B (k = 16) Target baud rate = 76,800 bps Baud rate = 2.
CHAPTER 13 SERIAL INTERFACE UART0 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 13-13.
CHAPTER 13 SERIAL INTERFACE UART0 Minimum permissible data frame length: FLmin = 11 × FL − k−2 2k × FL = 21k + 2 2k FL Therefore, the maximum receivable baud rate at the transmission destination is as follows. BRmax = (FLmin/11)−1 = 22k 21k + 2 Brate Similarly, the maximum permissible data frame length can be calculated as follows.
CHAPTER 14 SERIAL INTERFACE UART6 14.1 Functions of Serial Interface UART6 Serial interface UART6 has the following two modes. (1) Operation stop mode This mode is used when serial communication is not executed and can enable a reduction in the power consumption. For details, see 14.4.1 Operation stop mode. (2) Asynchronous serial interface (UART) mode This mode supports the LIN (Local Interconnect Network)-bus. The functions of this mode are outlined below. For details, see 14.4.
CHAPTER 14 SERIAL INTERFACE UART6 Remark LIN stands for Local Interconnect Network and is a low-speed (1 to 20 kbps) serial communication protocol intended to aid the cost reduction of an automotive network. LIN communication is single-master communication, and up to 15 slaves can be connected to one master. The LIN slaves are used to control the switches, actuators, and sensors, and these are connected to the LIN master via the LIN network.
CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-2. LIN Reception Operation Wakeup signal frame Sync break field Sync field Identifier field Data field Data field Checksum field 13-bit SBF reception SF reception ID reception Data reception Data reception LIN Bus <5> <2> RXD6 (input) Disable Data reception Enable <3> Reception interrupt (INTSR6) <1> Edge detection (INTP0) <4> Capture timer Disable Enable Reception processing is as follows.
CHAPTER 14 SERIAL INTERFACE UART6 Selector Selector Figure 14-3.
CHAPTER 14 SERIAL INTERFACE UART6 The peripheral functions used in the LIN communication operation are shown below. • External interrupt (INTP0); wakeup signal detection Use: Detects the wakeup signal edges and detects start of communication. • 16-bit timer/event counter 00 (TI000); baud rate error detection Use: Detects the baud rate error (measures the TI000 input edge interval in the capture mode) by detecting the sync field (SF) length and divides it by the number of bits.
340 Figure 14-4.
CHAPTER 14 SERIAL INTERFACE UART6 (1) Receive buffer register 6 (RXB6) This 8-bit register stores parallel data converted by receive shift register 6 (RXS6). Each time 1 byte of data has been received, new receive data is transferred to this register from RXS6. If the data length is set to 7 bits, data is transferred as follows. • In LSB-first reception, the receive data is transferred to bits 0 to 6 of RXB6 and the MSB of RXB6 is always 0.
CHAPTER 14 SERIAL INTERFACE UART6 14.3 Registers Controlling Serial Interface UART6 Serial interface UART6 is controlled by the following twelve registers.
CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-5. Format of Asynchronous Serial Interface Operation Mode Register 6 (ASIM6) (2/2) PS61 PS60 Transmission operation 0 0 Does not output parity bit. Reception without parity 0 1 Outputs 0 parity. Reception as 0 parity 1 0 Outputs odd parity. Judges as odd parity. 1 1 Outputs even parity. Judges as even parity.
CHAPTER 14 SERIAL INTERFACE UART6 (2) Asynchronous serial interface reception error status register 6 (ASIS6) This register indicates an error status on completion of reception by serial interface UART6. It includes three error flag bits (PE6, FE6, OVE6). This register is read-only by an 8-bit memory manipulation instruction. Reset signal generation, or clearing bit 7 (POWER6) or bit 5 (RXE6) of ASIM6 to 0 clears this register to 00H. 00H is read when this register is read.
CHAPTER 14 SERIAL INTERFACE UART6 (3) Asynchronous serial interface transmission status register 6 (ASIF6) This register indicates the status of transmission by serial interface UART6. It includes two status flag bits (TXBF6 and TXSF6). Transmission can be continued without disruption even during an interrupt period, by writing the next data to the TXB6 register after data has been transferred from the TXB6 register to the TXS6 register.
CHAPTER 14 SERIAL INTERFACE UART6 (4) Clock selection register 6 (CKSR6) This register selects the base clock of serial interface UART6. CKSR6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 00H. Remark CKSR6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1). Figure 14-8.
CHAPTER 14 SERIAL INTERFACE UART6 (5) Baud rate generator control register 6 (BRGC6) This register sets the division value of the 8-bit counter of serial interface UART6. BRGC6 can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH. Remark BRGC6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1). Figure 14-9.
CHAPTER 14 SERIAL INTERFACE UART6 (6) Asynchronous serial interface control register 6 (ASICL6) This register controls the serial communication operations of serial interface UART6. ASICL6 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 16H. Caution ASICL6 can be refreshed (the same value is written) by software during a communication operation (when bits 7 and 6 (POWER6, TXE6) of ASIM6 = 1 or bits 7 and 5 (POWER6, RXE6) of ASIM6 = 1).
CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-10. Format of Asynchronous Serial Interface Control Register 6 (ASICL6) (2/2) SBL62 SBL61 SBL60 SBF transmission output width control 1 0 1 SBF is output with 13-bit length. 1 1 0 SBF is output with 14-bit length. 1 1 1 SBF is output with 15-bit length. 0 0 0 SBF is output with 16-bit length. 0 0 1 SBF is output with 17-bit length. 0 1 0 SBF is output with 18-bit length. 0 1 1 SBF is output with 19-bit length.
CHAPTER 14 SERIAL INTERFACE UART6 (7) Input switch control register (ISC) By setting ISC5 to 1, the UART6 I/O pins are switched from P113/SEG7/RxD6 and P112/SEG6/TxD6 to P12/RxD0/KR3/RxD6 and P13/TxD0/KR4/TxD6. By setting ISC3 to 1, the P113/SEG7/RxD6 pin is enabled for input. When ISC3 is cleared to 0, external input is not acknowledged. Thus, after release of reset, a generation of a through current due to an undetermined input state until an output setting is performed is prevented.
CHAPTER 14 SERIAL INTERFACE UART6 Caution When using the P113/SEG7/RxD6 pin as the P113 or RxD6 pin, set PF11ALL to 0 and ISC3 to 1, after release of reset. When using the P113/SEG7/RxD6 pin as the SEG7 pin, set PF11ALL to 1 and ISC3 to 0, after release of reset. (8) Port function register 1 (PF1) This register sets the pin functions of P13/TxD0/KR4/TxD6 pin. PF1 is set using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PF1 to 00H. Figure 14-12.
CHAPTER 14 SERIAL INTERFACE UART6 (10) Port mode register 11 (PM11) This register sets port 11 input/output in 1-bit units. When using the P112/SEG6/TXD6 pin for serial interface data output, clear PM112 to 0 and set the output latch of P112 to 1. When using the P113/SEG7/RXD6 pin for serial interface data input, set PM113 to 1. The output latch of P113 at this time may be 0 or 1. PM11 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to FFH.
CHAPTER 14 SERIAL INTERFACE UART6 14.4 Operation of Serial Interface UART6 Serial interface UART6 has the following two modes. • Operation stop mode • Asynchronous serial interface (UART) mode 14.4.1 Operation stop mode In this mode, serial communication cannot be executed; therefore, the power consumption can be reduced. In addition, the pins can be used as ordinary port pins in this mode. To set the operation stop mode, clear bits 7, 6, and 5 (POWER6, TXE6, and RXE6) of ASIM6 to 0.
CHAPTER 14 SERIAL INTERFACE UART6 14.4.2 Asynchronous serial interface (UART) mode In this mode, data of 1 byte is transmitted/received following a start bit, and a full-duplex operation can be performed. A dedicated UART baud rate generator is incorporated, so that communication can be executed at a wide range of baud rates.
CHAPTER 14 SERIAL INTERFACE UART6 The relationship between the register settings and pins is shown below. Table 14-2.
CHAPTER 14 SERIAL INTERFACE UART6 (2) Communication operation (a) Format and waveform example of normal transmit/receive data Figures 14-15 and 14-16 show the format and waveform example of the normal transmit/receive data. Figure 14-15. Format of Normal UART Transmit/Receive Data 1. LSB-first transmission/reception 1 data frame Start bit D0 D1 D2 D3 D4 D5 D6 D7 Parity bit Stop bit D1 D0 Parity bit Stop bit Character bits 2.
CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-16. Example of Normal UART Transmit/Receive Data Waveform 1. Data length: 8 bits, LSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D0 D1 D2 D3 D4 D5 D6 D7 Parity Stop 2. Data length: 8 bits, MSB first, Parity: Even parity, Stop bit: 1 bit, Communication data: 55H 1 data frame Start D7 D6 D5 D4 D3 D2 D1 D0 Parity Stop 3.
CHAPTER 14 SERIAL INTERFACE UART6 (b) Parity types and operation The parity bit is used to detect a bit error in communication data. Usually, the same type of parity bit is used on both the transmission and reception sides. With even parity and odd parity, a 1-bit (odd number) error can be detected. With zero parity and no parity, an error cannot be detected. Caution Fix the PS61 and PS60 bits to 0 when the device is used in LIN communication operation.
CHAPTER 14 SERIAL INTERFACE UART6 (c) Normal transmission When bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and bit 6 (TXE6) of ASIM6 is then set to 1, transmission is enabled. Transmission can be started by writing transmit data to transmit buffer register 6 (TXB6). The start bit, parity bit, and stop bit are automatically appended to the data. When transmission is started, the data in TXB6 is transferred to transmit shift register 6 (TXS6).
CHAPTER 14 SERIAL INTERFACE UART6 (d) Continuous transmission The next transmit data can be written to transmit buffer register 6 (TXB6) as soon as transmit shift register 6 (TXS6) has started its shift operation. Consequently, even while the INTST6 interrupt is being serviced after transmission of one data frame, data can be continuously transmitted and an efficient communication rate can be realized.
CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-18 shows an example of the continuous transmission processing flow. Figure 14-18. Example of Continuous Transmission Processing Flow Set registers. Write TXB6. Transfer executed necessary number of times? Yes No Read ASIF6 TXBF6 = 0? No Yes Write TXB6.
CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-19 shows the timing of starting continuous transmission, and Figure 14-20 shows the timing of ending continuous transmission. Figure 14-19. Timing of Starting Continuous Transmission Start TXD6 Data (1) Parity Stop Start Data (2) Parity Stop Start INTST6 TXB6 FF TXS6 FF Data (1) Data (2) Data (1) Data (3) Data (2) Data (3) TXBF6 Note TXSF6 Note When ASIF6 is read, there is a period in which TXBF6 and TXSF6 = 1, 1.
CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-20.
CHAPTER 14 SERIAL INTERFACE UART6 (e) Normal reception Reception is enabled and the RXD6 pin input is sampled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1. The 8-bit counter of the baud rate generator starts counting when the falling edge of the RXD6 pin input is detected.
CHAPTER 14 SERIAL INTERFACE UART6 (f) Reception error Three types of errors may occur during reception: a parity error, framing error, or overrun error. If the error flag of asynchronous serial interface reception error status register 6 (ASIS6) is set as a result of data reception, a reception error interrupt request (INTSR6/INTSRE6) is generated.
CHAPTER 14 SERIAL INTERFACE UART6 (g) Noise filter of receive data The RxD6 signal is sampled with the base clock output by the prescaler block. If two sampled values are the same, the output of the match detector changes, and the data is sampled as input data. Because the circuit is configured as shown in Figure 14-23, the internal processing of the reception operation is delayed by two clocks from the external signal status. Figure 14-23.
CHAPTER 14 SERIAL INTERFACE UART6 (i) SBF reception When the device is used in LIN communication operation, the SBF (Synchronous Break Field) reception control function is used for reception. For the reception operation of LIN, see Figure 14-2 LIN Reception Operation. Reception is enabled when bit 7 (POWER6) of asynchronous serial interface operation mode register 6 (ASIM6) is set to 1 and then bit 5 (RXE6) of ASIM6 is set to 1.
CHAPTER 14 SERIAL INTERFACE UART6 14.4.3 Dedicated baud rate generator The dedicated baud rate generator consists of a source clock selector and an 8-bit programmable counter, and generates a serial clock for transmission/reception of UART6. Separate 8-bit counters are provided for transmission and reception.
CHAPTER 14 SERIAL INTERFACE UART6 Figure 14-26.
CHAPTER 14 SERIAL INTERFACE UART6 14.4.4 Calculation of baud rate (1) Baud rate calculation expression The baud rate can be calculated by the following expression. • Baud rate = fXCLK6 2×k [bps] fXCLK6: Frequency of base clock selected by TPS63 to TPS60 bits of CKSR6 register k: Value set by MDL67 to MDL60 bits of BRGC6 register (k = 4, 5, 6, ..., 255) Table 14-4.
CHAPTER 14 SERIAL INTERFACE UART6 (2) Error of baud rate The baud rate error can be calculated by the following expression. • Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) − 1 × 100 [%] Cautions 1. Keep the baud rate error during transmission to within the permissible error range at the reception destination. 2. Make sure that the baud rate error during reception satisfies the range shown in (4) Permissible baud rate range during reception.
CHAPTER 14 SERIAL INTERFACE UART6 (3) Example of setting baud rate Table 14-5. Set Data of Baud Rate Generator Baud Rate [bps] fPRS = 2.0 MHz TPS63- k TPS60 fPRS = 5.0 MHz Calculated ERR TPS63- Value [%] TPS60 k fPRS = 10.0 MHz Calculated ERR TPS63- Value [%] TPS60 k Calculated ERR Value [%] 300 8H 13 301 0.16 7H 65 301 0.16 8H 65 301 0.16 600 7H 13 601 0.16 6H 65 601 0.16 7H 65 601 0.16 1200 6H 13 1202 0.16 5H 65 1202 0.16 6H 65 1202 0.
CHAPTER 14 SERIAL INTERFACE UART6 (4) Permissible baud rate range during reception The permissible error from the baud rate at the transmission destination during reception is shown below. Caution Make sure that the baud rate error during reception is within the permissible error range, by using the calculation expression shown below. Figure 14-27.
CHAPTER 14 SERIAL INTERFACE UART6 Minimum permissible data frame length: FLmin = 11 × FL − k−2 2k × FL = 21k + 2 2k FL Therefore, the maximum receivable baud rate at the transmission destination is as follows. 22k BRmax = (FLmin/11)−1 = Brate 21k + 2 Similarly, the maximum permissible data frame length can be calculated as follows.
CHAPTER 14 SERIAL INTERFACE UART6 (5) Data frame length during continuous transmission When data is continuously transmitted, the data frame length from a stop bit to the next start bit is extended by two clocks of base clock from the normal value. However, the result of communication is not affected because the timing is initialized on the reception side when the start bit is detected. Figure 14-28.
CHAPTER 15 LCD CONTROLLER/DRIVER 15.1 Functions of LCD Controller/Driver The functions of the LCD controller/driver in the 78K0/LC3 are as follows. (1) The LCD driver voltage generator can switch external resistance division and internal resistance division.
CHAPTER 15 LCD CONTROLLER/DRIVER Table 15-1 lists the maximum number of pixels that can be displayed in each display mode. Table 15-1.
CHAPTER 15 LCD CONTROLLER/DRIVER 15.2 Configuration of LCD Controller/Driver The LCD controller/driver consists of the following hardware. Table 15-2.
Figure 15-1.
CHAPTER 15 LCD CONTROLLER/DRIVER 15.3 Registers Controlling LCD Controller/Driver The following five registers are used to control the LCD controller/driver. • LCD mode register (LCDMD) • LCD display mode register (LCDM) • LCD clock control register (LCDC0) • Port function register 2 (PF2) • Port function register ALL (PFALL) (1) LCD mode register (LCDMD) LCDMD sets the LCD drive voltage generator. LCDMD is set using a 1-bit or 8-bit memory manipulation instruction.
CHAPTER 15 LCD CONTROLLER/DRIVER (2) LCD display mode register (LCDM) LCDM specifies whether to enable display operation. It also specifies whether to enable segment pin/common pin output, gate booster circuit control, and the display mode. LCDM is set using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets LCDM to 00H. Figure 15-3.
CHAPTER 15 LCD CONTROLLER/DRIVER Notes 1. When LCD display is not performed or necessary, set SCOC and VAON to 0, in order to reduce power consumption. 2. This bit is used to control boosting of the internal gate signal of the LCD controller/driver. If set to "Internal gate voltage boosting", the LCD drive performance can be enhanced. Set VAON based on the following conditions. • When 2.0 V ≤ VLCD ≤ VDD ≤ 5.5 V: VAON = 0 • When 1.8 V ≤ VLCD ≤ VDD ≤ 3.
CHAPTER 15 LCD CONTROLLER/DRIVER (3) LCD clock control register (LCDC0) LCDC0 specifies the LCD source clock and LCD clock. The frame frequency is determined according to the LCD clock and the number of time slices. LCDC0 is set using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets LCDC0 to 00H. Figure 15-4.
CHAPTER 15 LCD CONTROLLER/DRIVER (4) Port function register 2 (PF2) This register sets whether to use pins P20 to P25 as port pins (other than segment output pins) or segment output pins. PF2 is set using a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PF2 to 00H. Figure 15-5.
CHAPTER 15 LCD CONTROLLER/DRIVER 15.4 Setting LCD Controller/Driver Set the LCD controller/driver using the following procedure. <1> Set (VAON = 1) internal gate voltage boosting (bit 4 of the LCD display mode register (LCDM)) <2> Set the resistance division method via MDSET0 and MDSET1 (bits 4 and 5 of the LCD mode register (LCDMD)) (MDSET0 = 0: external resistance division method, MDSET0 = 1: internal resistance division method).
CHAPTER 15 LCD CONTROLLER/DRIVER 15.5 LCD Display Data Memory The LCD display data memory is mapped at addresses FA40H to FA55H. Data in the LCD display data memory can be displayed on the LCD panel using the LCD controller/driver. Figure 15-7 shows the relationship between the contents of the LCD display data memory and the segment/common outputs. The areas not to be used for display can be used as normal RAM. Figure 15-7.
CHAPTER 15 LCD CONTROLLER/DRIVER 15.6 Common and Segment Signals Each pixel of the LCD panel turns on when the potential difference between the corresponding common and segment signals becomes higher than a specific voltage (LCD drive voltage, VLCD). The pixels turn off when the potential difference becomes lower than VLCD. Applying DC voltage to the common and segment signals of an LCD panel causes deterioration. To avoid this problem, this LCD panel is driven by AC voltage.
CHAPTER 15 LCD CONTROLLER/DRIVER (3) Output waveforms of common and segment signals The voltages listed in Table 15-4 are output as common and segment signals. When both common and segment signals are at the select voltage, a display on-voltage of ±VLCD is obtained. The other combinations of the signals correspond to the display off-voltage. Table 15-4.
CHAPTER 15 LCD CONTROLLER/DRIVER Figure 15-8 shows the common signal waveforms, and Figure 15-9 shows the voltages and phases of the common and segment signals. Figure 15-8.
CHAPTER 15 LCD CONTROLLER/DRIVER (d) 1/4 bias method VLC0 VLC1 COMn VLC2 VLC3 (Eight-time slot mode) LVSS TF = 8 × T T: One LCD clock period 390 TF: Frame frequency User’s Manual U18698EJ1V0UD VLCD
CHAPTER 15 LCD CONTROLLER/DRIVER Figure 15-9.
CHAPTER 15 LCD CONTROLLER/DRIVER (d) 1/4 bias method Select Deselect VLC0 VLC1 VLC2 Common signal VLCD VLC3 LVSS VLC0 VLC1 VLC2 Segment signal VLC3 LVSS T T T T: One LCD clock period 392 User’s Manual U18698EJ1V0UD T VLCD
CHAPTER 15 LCD CONTROLLER/DRIVER 15.7 Display Modes 15.7.1 Static display example Figure 15-11 shows how the three-digit LCD panel having the display pattern shown in Figure 15-10 is connected to the segment signals (SEG0 to SEG21) and the common signal (COM0) of the 78K0/LC3 chip. This example displays data "2.3" in the LCD panel. The contents of the display data memory (FA40H to FA55H) correspond to this display. The following description focuses on numeral "2." ( ) displayed in the second digit.
CHAPTER 15 LCD CONTROLLER/DRIVER Figure 15-11.
CHAPTER 15 LCD CONTROLLER/DRIVER Figure 15-12.
CHAPTER 15 LCD CONTROLLER/DRIVER 15.7.2 Two-time-slice display example Figure 15-14 shows how the 6-digit LCD panel having the display pattern shown in Figure 15-13 is connected to the segment signals (SEG0 to SEG22) and the common signals (COM0 and COM1) of the 78K0/LC3 chip. This example displays data "2345.6" in the LCD panel. The contents of the display data memory (FA40H to FA55H) correspond to this display. The following description focuses on numeral "3" ( ) displayed in the fourth digit.
CHAPTER 15 LCD CONTROLLER/DRIVER Timing strobe Figure 15-14.
CHAPTER 15 LCD CONTROLLER/DRIVER Figure 15-15.
CHAPTER 15 LCD CONTROLLER/DRIVER 15.7.3 Three-time-slice display example Figure 15-17 shows how the 8-digit LCD panel having the display pattern shown in Figure 15-16 is connected to the segment signals (SEG0 to SEG22) and the common signals (COM0 to COM2) of the 78K0/LC3 chip. This example displays data "23456.78" in the LCD panel. The contents of the display data memory (addresses FA40H to FA55H) correspond to this display. The following description focuses on numeral "6.
CHAPTER 15 LCD CONTROLLER/DRIVER Figure 15-17. Example of Connecting Three-Time-Slice LCD Panel Timing strobe COM 3 COM 2 COM 1 x 5 x 6 x 7 x 8 x 9 x A x B x C x D x E x F x 2 x 3 FA54H x 1 x FA50H SEG 0 SEG 1 SEG 2 SEG 3 SEG 4 SEG 5 SEG 6 SEG 7 SEG 8 SEG 9 SEG 10 SEG 11 SEG 12 SEG 13 SEG 14 SEG 15 SEG 16 SEG 17 SEG 18 SEG 19 SEG 20 ×’: Can be used to store any data because there is no corresponding segment in the LCD panel.
CHAPTER 15 LCD CONTROLLER/DRIVER Figure 15-18.
CHAPTER 15 LCD CONTROLLER/DRIVER Figure 15-19.
CHAPTER 15 LCD CONTROLLER/DRIVER 15.7.4 Four-time-slice display example Figure 15-21 shows how the 12-digit LCD panel having the display pattern shown in Figure 15-20 is connected to the segment signals (SEG0 to SEG21) and the common signals (COM0 to COM3) of the 78K0/LC3 chip. This example displays data "23456.789012" in the LCD panel. The contents of the display data memory (addresses FA40H to FA55H) correspond to this display. The following description focuses on numeral "6.
CHAPTER 15 LCD CONTROLLER/DRIVER Figure 15-21.
CHAPTER 15 LCD CONTROLLER/DRIVER Figure 15-22. Four-Time-Slice LCD Drive Waveform Examples (1/3 Bias Method) TF VLC0 VLC1 COM0 VLC2 LVSS VLC0 VLC1 COM1 VLC2 LVSS VLC0 VLC1 COM2 VLC2 LVSS VLC0 VLC1 COM3 VLC2 LVSS VLC0 VLC1 SEG12 VLC2 LVSS +VLCD +1/3VLCD COM0-SEG12 0 -1/3VLCD -VLCD +VLCD +1/3VLCD 0 COM1-SEG12 -1/3VLCD -VLCD Remark The waveforms for COM2 to SEG12 and COM3 to SEG12 are omitted.
CHAPTER 15 LCD CONTROLLER/DRIVER 15.8 Supplying LCD Drive Voltages VLC0, VLC1, VLC2 and VLC3 With the 78K0/LC3, a LCD drive power supply can be generated using either of two types of methods: internal resistance division method or external resistance division method. 15.8.1 Internal resistance division method The 78K0/LC3 incorporates voltage divider resistors for generating LCD drive power supplies.
CHAPTER 15 LCD CONTROLLER/DRIVER Figure 15-23.
CHAPTER 15 LCD CONTROLLER/DRIVER 15.8.2 External resistance division method The 78K0/LC3 can also use external voltage divider resistors for generating LCD drive power supplies, without using internal resistors. Figure 15-24 shows examples of LCD drive voltage connection, corresponding to each bias method. Figure 15-24.
CHAPTER 15 LCD CONTROLLER/DRIVER Figure 15-24.
CHAPTER 16 MANCHESTER CODE GENERATOR 16.1 Functions of Manchester Code Generator The following three types of modes are available for the Manchester code generator. (1) Operation stop mode This mode is used when output by the Manchester code generator/bit sequential buffer is not performed. This mode reduces the power consumption. For details, refer to 16.4.1 Operation stop mode. (2) Manchester code generator mode This mode is used to transmit Manchester code from the MCGO pin.
CHAPTER 16 MANCHESTER CODE GENERATOR Figure 16-1.
CHAPTER 16 MANCHESTER CODE GENERATOR (2) MCG transmit bit count specification register (MC0BIT) This register is used to set the number of transmit bits. Set the transmit bit count to this register before setting the transmit data to MC0TX. In continuous transmission, the number of transmit bits to be transmitted next needs to be written after the occurrence of a transmission start interrupt (INTMCG).
CHAPTER 16 MANCHESTER CODE GENERATOR 16.3 Registers Controlling Manchester Code Generator The following six types of registers are used to control the Manchester code generator. • MCG control register 0 (MC0CTL0) • MCG control register 1 (MC0CTL1) • MCG control register 2 (MC0CTL2) • MCG status register (MC0STR) • Port mode register 3 (PM3) • Port register 3 (P3) (1) MCG control register 0 (MC0CTL0) This register is used to set the operation mode and to enable/disable the operation.
CHAPTER 16 MANCHESTER CODE GENERATOR (2) MCG control register 1 (MC0CTL1) This register is used to set the base clock of the Manchester code generator. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Figure 16-5.
CHAPTER 16 MANCHESTER CODE GENERATOR (3) MCG control register 2 (MC0CTL2) This register is used to set the transmit baud rate. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 1FH. Figure 16-6.
CHAPTER 16 MANCHESTER CODE GENERATOR Figure 16-7. Format of MCG Status Register (MC0STR) Address: FF47H After reset: 00H R Symbol <7> 6 5 4 3 2 1 0 MC0STR MC0TSF 0 0 0 0 0 0 0 MC0TSF Data transmission status • Reset signal generation 0 • MC0PWR = 0 • If the next transfer data is not written to MC0TX when a transmission is completed 1 Transmission operation in progress Caution This flag always indicates 1 during continuous transmission.
CHAPTER 16 MANCHESTER CODE GENERATOR 16.4.2 Manchester code generator mode This mode is used to transmit data in Manchester code format using the MCGO pin. (1) Register description MCG control register 0 (MC0CTL0), MCG control register 1 (MC0CTL1), and MCG control register 2 (MC0CTL2) are used to set the Manchester code generator mode. (a) MCG control register 0 (MC0CTL0) This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 10H.
CHAPTER 16 MANCHESTER CODE GENERATOR (b) MCG control register 1 (MC0CTL1) This register is used to set the base clock of the Manchester code generator. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Address: FF4DH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 MC0CTL1 0 0 0 0 0 MC0CKS2 MC0CKS1 MC0CKS0 MC0CKS2 MC0CKS1 MC0CKS0 0 0 0 fPRS 0 0 1 fPRS/2 (5 MHz) 0 1 0 fPRS/2 (2.5 MHz) 0 1 1 fPRS/2 (1.
CHAPTER 16 MANCHESTER CODE GENERATOR (c) MCG control register 2 (MC0CTL2) This register is used to set the transmit baud rate. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 1FH.
CHAPTER 16 MANCHESTER CODE GENERATOR <2> Error of baud rate The baud rate error can be calculated by the following expression. • Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) − 1 × 100 [%] Caution Keep the baud rate error during transmission to within the permissible error range at the reception destination. Example: Frequency of base clock = 2.
CHAPTER 16 MANCHESTER CODE GENERATOR (d) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P32/TOH0/MCGO pin for Manchester code output, clear PM32 to 0 and clear the output latch of P32 to 0. PM3 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH.
CHAPTER 16 MANCHESTER CODE GENERATOR (3) Transmit operation In Manchester code generator mode, data is transmitted in 1- to 8-bit units. Data bits are transmitted in Manchester code format. Transmission is enabled if bit 7 (MC0PWR) of MCG control register 0 (MC0CTL0) is set to 1. The output value while a transmission is suspended can be set by using bit 0 (MC0OLV) of the MC0CTL0 register.
CHAPTER 16 MANCHESTER CODE GENERATOR Figure 16-8.
CHAPTER 16 MANCHESTER CODE GENERATOR Figure 16-8.
CHAPTER 16 MANCHESTER CODE GENERATOR Figure 16-8.
CHAPTER 16 MANCHESTER CODE GENERATOR 16.4.3 Bit sequential buffer mode The bit sequential buffer mode is used to output sequential signals using the MCGO pin. (1) Register description The MCG control register 0 (MC0CTL0), MCG control register 1 (MC0CTL1), and MCG control register 2 (MC0CTL2) are used to set the bit sequential buffer mode. (a) MCG control register 0 (MC0CTL0) This register can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets this register to 10H.
CHAPTER 16 MANCHESTER CODE GENERATOR (b) MCG control register 1 (MC0CTL1) This register is used to set the base clock of the Manchester code generator. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation clears this register to 00H. Address: FF4DH After reset: 00H R/W Symbol 7 6 5 4 3 2 1 0 MC0CTL1 0 0 0 0 0 MC0CKS2 MC0CKS1 MC0CKS0 MC0CKS2 MC0CKS1 MC0CKS0 0 0 0 fPRS (10 MHz) 0 0 1 fPRS/2 (5 MHz) 0 1 0 fPRS/2 (2.
CHAPTER 16 MANCHESTER CODE GENERATOR (c) MCG control register 2 (MC0CTL2) This register is used to set the transmit baud rate. This register can be set by an 8-bit memory manipulation instruction. Reset signal generation sets this register to 1FH.
CHAPTER 16 MANCHESTER CODE GENERATOR <2> Error of baud rate The baud rate error can be calculated by the following expression. • Error (%) = Actual baud rate (baud rate with error) Desired baud rate (correct baud rate) − 1 × 100 [%] Caution Keep the baud rate error during transmission to within the permissible error range at the reception destination. Example: Frequency of base clock = 2.
CHAPTER 16 MANCHESTER CODE GENERATOR (d) Port mode register 3 (PM3) This register sets port 3 input/output in 1-bit units. When using the P32/TOH0/MCGO pin for bit sequential data output, clear PM32 to 0 and clear the output latch of P32 to 0. PM3 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets these registers to FFH.
CHAPTER 16 MANCHESTER CODE GENERATOR (2) Transmit operation In bit sequential buffer mode, data is transmitted in 1- to 8-bit units. Transmission is enabled if bit 7 (MC0PWR) of MCG control register 0 (MC0CTL0) is set to 1. The output value while transmission is suspended can be set by using bit 0 (MC0OLV) of the MC0CTL0 register.
CHAPTER 16 MANCHESTER CODE GENERATOR Figure 16-9.
CHAPTER 16 MANCHESTER CODE GENERATOR Figure 16-9.
CHAPTER 16 MANCHESTER CODE GENERATOR Figure 16-9.
CHAPTER 17 INTERRUPT FUNCTIONS 17.1 Interrupt Function Types The following two types of interrupt functions are used. (1) Maskable interrupts These interrupts undergo mask control. Maskable interrupts can be divided into a high interrupt priority group and a low interrupt priority group by setting the priority specification flag registers (PR0L, PR0H, PR1L, PR1H). Multiple interrupt servicing can be applied to low-priority interrupts when high-priority interrupts are generated.
CHAPTER 17 INTERRUPT FUNCTIONS Table 17-1.
CHAPTER 17 INTERRUPT FUNCTIONS Table 17-1.
CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-1.
CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-1.
CHAPTER 17 INTERRUPT FUNCTIONS 17.3 Registers Controlling Interrupt Functions The following 6 types of registers are used to control the interrupt functions.
CHAPTER 17 INTERRUPT FUNCTIONS (1) Interrupt request flag registers (IF0L, IF0H, IF1L, IF1H) The interrupt request flags are set to 1 when the corresponding interrupt request is generated or an instruction is executed. They are cleared to 0 when an instruction is executed upon acknowledgment of an interrupt request or upon reset signal generation. When an interrupt is acknowledged, the interrupt request flag is automatically cleared and then the interrupt routine is entered.
CHAPTER 17 INTERRUPT FUNCTIONS Cautions 3. When manipulating a flag of the interrupt request flag register, use a 1-bit memory manipulation instruction (CLR1). When describing in C language, use a bit manipulation instruction such as “IF0L.0 = 0;” or “_asm(“clr1 IF0L, 0”);” because the compiled assembler must be a 1-bit memory manipulation instruction (CLR1).
CHAPTER 17 INTERRUPT FUNCTIONS (2) Interrupt mask flag registers (MK0L, MK0H, MK1L, MK1H) The interrupt mask flags are used to enable/disable the corresponding maskable interrupt servicing. MK0L, MK0H, MK1L, and MK1H are set by a 1-bit or 8-bit memory manipulation instruction. When MK0L and MK0H, and MK1L and MK1H are combined to form 16-bit registers MK0 and MK1, they are set by a 16-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 17-3.
CHAPTER 17 INTERRUPT FUNCTIONS (3) Priority specification flag registers (PR0L, PR0H, PR1L, PR1H) The priority specification flag registers are used to set the corresponding maskable interrupt priority order. PR0L, PR0H, PR1L, and PR1H are set by a 1-bit or 8-bit memory manipulation instruction. If PR0L and PR0H, and PR1L and PR1H are combined to form 16-bit registers PR0 and PR1, they are set by a 16-bit memory manipulation instruction. Reset signal generation sets these registers to FFH. Figure 17-4.
CHAPTER 17 INTERRUPT FUNCTIONS (4) External interrupt rising edge enable register (EGP), external interrupt falling edge enable register (EGN) These registers specify the valid edge for INTP0 to INTP3. EGP and EGN are set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears these registers to 00H. Figure 17-5.
CHAPTER 17 INTERRUPT FUNCTIONS (5) Program status word (PSW) The program status word is a register used to hold the instruction execution result and the current status for an interrupt request. The IE flag that sets maskable interrupt enable/disable and the ISP flag that controls multiple interrupt servicing are mapped to the PSW. Besides 8-bit read/write, this register can carry out operations using bit manipulation instructions and dedicated instructions (EI and DI).
CHAPTER 17 INTERRUPT FUNCTIONS 17.4 Interrupt Servicing Operations 17.4.1 Maskable interrupt acknowledgment A maskable interrupt becomes acknowledgeable when the interrupt request flag is set to 1 and the mask (MK) flag corresponding to that interrupt request is cleared to 0. A vectored interrupt request is acknowledged if interrupts are in the interrupt enabled state (when the IE flag is set to 1).
CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-7.
CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-8. Interrupt Request Acknowledgment Timing (Minimum Time) 6 clocks CPU processing Instruction PSW and PC saved, jump to interrupt servicing Instruction Interrupt servicing program ××IF (××PR = 1) 8 clocks ××IF (××PR = 0) 7 clocks Remark 1 clock: 1/fCPU (fCPU: CPU clock) Figure 17-9.
CHAPTER 17 INTERRUPT FUNCTIONS 17.4.3 Multiple interrupt servicing Multiple interrupt servicing occurs when another interrupt request is acknowledged during execution of an interrupt. Multiple interrupt servicing does not occur unless the interrupt request acknowledgment enabled state is selected (IE = 1). When an interrupt request is acknowledged, interrupt request acknowledgment becomes disabled (IE = 0).
CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-10. Examples of Multiple Interrupt Servicing (1/2) Example 1. Multiple interrupt servicing occurs twice Main processing INTxx servicing INTyy servicing IE = 0 EI IE = 0 IE = 0 EI INTxx (PR = 1) INTzz servicing EI INTyy (PR = 0) INTzz (PR = 0) RETI IE = 1 RETI IE = 1 RETI IE = 1 During servicing of interrupt INTxx, two interrupt requests, INTyy and INTzz, are acknowledged, and multiple interrupt servicing takes place.
CHAPTER 17 INTERRUPT FUNCTIONS Figure 17-10. Examples of Multiple Interrupt Servicing (2/2) Example 3.
CHAPTER 17 INTERRUPT FUNCTIONS 17.4.4 Interrupt request hold There are instructions where, even if an interrupt request is issued for them while another instruction is being executed, request acknowledgment is held pending until the end of execution of the next instruction. These instructions (interrupt request hold instructions) are listed below. • MOV PSW, #byte • MOV A, PSW • MOV PSW, A • MOV1 PSW. bit, CY • MOV1 CY, PSW. bit • AND1 CY, PSW. bit • OR1 CY, PSW. bit • XOR1 CY, PSW. bit • SET1 PSW.
CHAPTER 18 KEY INTERRUPT FUNCTION 18.1 Functions of Key Interrupt A key interrupt (INTKR) can be generated by setting the key return mode register (KRM) and inputting a falling edge to the key interrupt input pins (KR0, KR3, and KR4). Table 18-1. Assignment of Key Interrupt Detection Pins Flag Description KRM0 Controls KR0 signal in 1-bit units. KRM3 Controls KR3 signal in 1-bit units. KRM4 Controls KR4 signal in 1-bit units. 18.
CHAPTER 18 KEY INTERRUPT FUNCTION 18.3 Register Controlling Key Interrupt (1) Key return mode register (KRM) This register controls the KRM0, KRM3, and KRM4 bits using the KR0, KR3, and KR4 signals, respectively. KRM is set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation clears KRM to 00H. Figure 18-2.
CHAPTER 19 STANDBY FUNCTION 19.1 Standby Function and Configuration 19.1.1 Standby function The standby function is designed to reduce the operating current of the system. The following two modes are available. (1) HALT mode HALT instruction execution sets the HALT mode. In the HALT mode, the CPU operation clock is stopped.
CHAPTER 19 STANDBY FUNCTION 19.1.2 Registers controlling standby function The standby function is controlled by the following two registers. • Oscillation stabilization time counter status register (OSTC) • Oscillation stabilization time select register (OSTS) Remark For the registers that start, stop, or select the clock, see CHAPTER 5 CLOCK GENERATOR.
CHAPTER 19 STANDBY FUNCTION (2) Oscillation stabilization time select register (OSTS) This register is used to select the X1 clock oscillation stabilization wait time when the STOP mode is released. When the X1 clock is selected as the CPU clock, the operation waits for the time set using OSTS after the STOP mode is released.
CHAPTER 19 STANDBY FUNCTION 19.2 Standby Function Operation 19.2.1 HALT mode (1) HALT mode The HALT mode is set by executing the HALT instruction. HALT mode can be set regardless of whether the CPU clock before the setting was the high-speed system clock, internal high-speed oscillation clock, or subsystem clock. The operating statuses in the HALT mode are shown below.
CHAPTER 19 STANDBY FUNCTION Table 19-1.
CHAPTER 19 STANDBY FUNCTION Table 19-1.
CHAPTER 19 STANDBY FUNCTION (2) HALT mode release The HALT mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the HALT mode is released. If interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 19-3.
CHAPTER 19 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, HALT mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 19-4.
CHAPTER 19 STANDBY FUNCTION Table 19-2. Operation in Response to Interrupt Request in HALT Mode Release Source Maskable interrupt MK×× PR×× IE ISP 0 0 0 × request Operation Next address instruction execution 0 0 1 × 0 1 0 1 Next address 0 1 × 0 instruction execution 0 1 1 1 Interrupt servicing Interrupt servicing execution execution Reset 1 × × × HALT mode held − − × × Reset processing ×: don’t care 19.2.
CHAPTER 19 STANDBY FUNCTION Table 19-3.
CHAPTER 19 STANDBY FUNCTION Cautions 1. To use the peripheral hardware that stops operation in the STOP mode, and the peripheral hardware for which the clock that stops oscillating in the STOP mode after the STOP mode is released, restart the peripheral hardware. 2. Even if “internal low-speed oscillator can be stopped by software” is selected by the option byte, the internal low-speed oscillation clock continues in the STOP mode in the status before the STOP mode is set.
CHAPTER 19 STANDBY FUNCTION The STOP mode can be released by the following two sources. (a) Release by unmasked interrupt request When an unmasked interrupt request is generated, the STOP mode is released. After the oscillation stabilization time has elapsed, if interrupt acknowledgment is enabled, vectored interrupt servicing is carried out. If interrupt acknowledgment is disabled, the next address instruction is executed. Figure 19-6.
CHAPTER 19 STANDBY FUNCTION Figure 19-6.
CHAPTER 19 STANDBY FUNCTION (b) Release by reset signal generation When the reset signal is generated, STOP mode is released, and then, as in the case with a normal reset operation, the program is executed after branching to the reset vector address. Figure 19-7.
CHAPTER 20 RESET FUNCTION The following four operations are available to generate a reset signal. (1) External reset input via RESET pin (2) Internal reset by watchdog timer program loop detection (3) Internal reset by comparison of supply voltage and detection voltage of power-on-clear (POC) circuit (4) Internal reset by comparison of supply voltage and detection voltage of low-power-supply detector (LVI) External and internal resets have no functional differences.
Figure 20-1. Block Diagram of Reset Function Internal bus Reset control flag register (RESF) WDTRF LVIRF Set Set Watchdog timer reset signal Clear Reset signal to LVIM/LVIS register Power-on-clear circuit reset signal Low-voltage detector reset signal Caution An LVI circuit internal reset does not reset the LVI circuit. Remarks 1. LVIM: Low-voltage detection register 2.
CHAPTER 20 RESET FUNCTION Figure 20-2. Timing of Reset by RESET Input Wait for oscillation accuracy stabilization (86 to 361 μs) Internal high-speed oscillation clock Starting X1 oscillation is specified by software. High-speed system clock (when X1 oscillation is selected) CPU clock Reset period (oscillation stop) Normal operation Reset processing (11 to 47 μ s) Normal operation (internal high-speed oscillation clock) RESET Internal reset signal Delay Delay (5 μ s (TYP.
CHAPTER 20 RESET FUNCTION Figure 20-4. Timing of Reset in STOP Mode by RESET Input Wait for oscillation accuracy stabilization (86 to 361 μs) STOP instruction execution Internal high-speed oscillation clock Starting X1 oscillation is specified by software.
CHAPTER 20 RESET FUNCTION Table 20-1. Operation Statuses During Reset Period Item During Reset Period System clock Clock supply to the CPU is stopped.
CHAPTER 20 RESET FUNCTION Table 20-2. Hardware Statuses After Reset Acknowledgment (1/3) Hardware After Reset Note 1 Acknowledgment Program counter (PC) The contents of the reset vector table (0000H, 0001H) are set.
CHAPTER 20 RESET FUNCTION Table 20-2.
CHAPTER 20 RESET FUNCTION Table 20-2.
CHAPTER 20 RESET FUNCTION 20.1 Register for Confirming Reset Source Many internal reset generation sources exist in the 78K0/LC3. The reset control flag register (RESF) is used to store which source has generated the reset request. RESF can be read by an 8-bit memory manipulation instruction. RESET input, reset by power-on-clear (POC) circuit, and reading RESF set RESF to 00H. Figure 20-5.
CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.1 Functions of Power-on-Clear Circuit The power-on-clear circuit (POC) has the following functions. • Generates internal reset signal at power on. In the 1.59 V POC mode (option byte: POCMODE = 0), the reset signal is released when the supply voltage (VDD) exceeds 1.59 V ±0.15 V. In the 2.7 V/1.59 V POC mode (option byte: POCMODE = 1), the reset signal is released when the supply voltage (VDD) exceeds 2.7 V ±0.2 V.
CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.2 Configuration of Power-on-Clear Circuit The block diagram of the power-on-clear circuit is shown in Figure 21-1. Figure 21-1. Block Diagram of Power-on-Clear Circuit VDD VDD + Internal reset signal − Reference voltage source 21.3 Operation of Power-on-Clear Circuit (1) In 1.59 V POC mode (option byte: POCMODE = 0) • An internal reset signal is generated on power application. When the supply voltage (VDD) exceeds the detection voltage (VPOC = 1.59 V ±0.
CHAPTER 21 POWER-ON-CLEAR CIRCUIT Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (1/2) (1) In 1.59 V POC mode (option byte: POCMODE = 0) Set LVI to be used for reset Set LVI to be used for interrupt Set LVI to be used for reset Supply voltage (VDD) VLVI 1.8 VNote 1 VPOC = 1.59 V (TYP.) 0.5 V/ms (MIN.
CHAPTER 21 POWER-ON-CLEAR CIRCUIT Figure 21-2. Timing of Generation of Internal Reset Signal by Power-on-Clear Circuit and Low-Voltage Detector (2/2) (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Set LVI to be used for reset Set LVI to be used for interrupt Set LVI to be used for reset Wait for oscillation accuracy stabilization (86 to 361 μs) Wait for oscillation accuracy stabilization (86 to 361 μs) Supply voltage (VDD) VLVI VDDPOC = 2.7 V (TYP.) 1.8 VNote 1 VPOC = 1.59 V (TYP.
CHAPTER 21 POWER-ON-CLEAR CIRCUIT 21.4 Cautions for Power-on-Clear Circuit In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the POC detection voltage (VPOC), the system may be repeatedly reset and released from the reset status. In this case, the time from release of reset to the start of the operation of the microcontroller can be arbitrarily set by taking the following action.
CHAPTER 21 POWER-ON-CLEAR CIRCUIT Figure 21-3.
CHAPTER 22 LOW-VOLTAGE DETECTOR 22.1 Functions of Low-Voltage Detector The low-voltage detector (LVI) has the following functions. • The LVI circuit compares the supply voltage (VDD) with the detection voltage (VLVI) or the input voltage from an external input pin (EXLVI) with the detection voltage (VEXLVI = 1.21 V (TYP.): fixed), and generates an internal reset or internal interrupt signal. • The supply voltage (VDD) or input voltage from an external input pin (EXLVI) can be selected by software.
CHAPTER 22 LOW-VOLTAGE DETECTOR 22.2 Configuration of Low-Voltage Detector The block diagram of the low-voltage detector is shown in Figure 22-1. Figure 22-1.
CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-2.
CHAPTER 22 LOW-VOLTAGE DETECTOR (2) Low-voltage detection level selection register (LVIS) This register selects the low-voltage detection level. This register can be set by a 1-bit or 8-bit memory manipulation instruction. The generation of a reset signal other than an LVI reset clears this register to 00H. Figure 22-3.
CHAPTER 22 LOW-VOLTAGE DETECTOR (3) Port mode register 12 (PM12) When using the P120/EXLVI/INTP0 pin for external low-voltage detection potential input, set PM120 to 1. At this time, the output latch of P120 may be 0 or 1. PM12 can be set by a 1-bit or 8-bit memory manipulation instruction. Reset signal generation sets PM12 to FFH. Figure 22-4.
CHAPTER 22 LOW-VOLTAGE DETECTOR 22.4.1 When used as reset (1) When detecting level of supply voltage (VDD) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage (VDD)) (default value). <3> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection register (LVIS). <4> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (VDD)) (1/2) (1) In 1.59 V POC mode (option byte: POCMODE = 0) Supply voltage (VDD) VLVI VPOC = 1.59 V (TYP.
CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-5. Timing of Low-Voltage Detector Internal Reset Signal Generation (Detects Level of Supply Voltage (VDD)) (2/2) (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Supply voltage (VDD) VLVI 2.7 V (TYP.) VPOC = 1.59 V (TYP.
CHAPTER 22 LOW-VOLTAGE DETECTOR (2) When detecting level of input voltage from external input pin (EXLVI) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)). <3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <4> Use software to wait for an operation stabilization time (10 μs (MAX.)).
CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-6.
CHAPTER 22 LOW-VOLTAGE DETECTOR 22.4.2 When used as interrupt (1) When detecting level of supply voltage (VDD) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Clear bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 0 (detects level of supply voltage (VDD)) (default value). <3> Set the detection voltage using bits 3 to 0 (LVIS3 to LVIS0) of the low-voltage detection level selection register (LVIS). <4> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation).
CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-7. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Supply Voltage (VDD)) (1/2) (1) In 1.59 V POC mode (option byte: POCMODE = 0) Supply voltage (VDD) VLVI VPOC = 1.59 V (TYP.
CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-7. Timing of Low-Voltage Detector Interrupt Signal Generation (Detects Level of Supply Voltage (VDD)) (2/2) (2) In 2.7 V/1.59 V POC mode (option byte: POCMODE = 1) Supply voltage (VDD) VLVI 2.7 V(TYP.) VPOC = 1.59 V (TYP.
CHAPTER 22 LOW-VOLTAGE DETECTOR (2) When detecting level of input voltage from external input pin (EXLVI) • When starting operation <1> Mask the LVI interrupt (LVIMK = 1). <2> Set bit 2 (LVISEL) of the low-voltage detection register (LVIM) to 1 (detects level of input voltage from external input pin (EXLVI)). <3> Set bit 7 (LVION) of LVIM to 1 (enables LVI operation). <4> Use software to wait for an operation stabilization time (10 μs (MAX.)).
CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-8.
CHAPTER 22 LOW-VOLTAGE DETECTOR 22.5 Cautions for Low-Voltage Detector In a system where the supply voltage (VDD) fluctuates for a certain period in the vicinity of the LVI detection voltage (VLVI), the operation is as follows depending on how the low-voltage detector is used. (1) When used as reset The system may be repeatedly reset and released from the reset status.
CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-9. Example of Software Processing After Reset Release (1/2) • If supply voltage fluctuation is 50 ms or less in vicinity of LVI detection voltage Reset ; Check the reset sourceNote Initialize the port. Initialization processing <1> LVI reset ; fPRS = Internal high-speed oscillation clock (8.4 MHz (MAX.)) (default) Source: fPRS (8.4 MHz (MAX.))/212, Where comparison value = 102: ≅ 50 ms Timer starts (TMHE1 = 1).
CHAPTER 22 LOW-VOLTAGE DETECTOR Figure 22-9.
CHAPTER 23 OPTION BYTE 23.1 Functions of Option Bytes The flash memory at 0080H to 0084H of the 78K0/LC3 is an option byte area. When power is turned on or when the device is restarted from the reset status, the device automatically references the option bytes and sets specified functions. When using the product, be sure to set the following functions by using the option bytes. When the boot swap operation is used during self-programming, 0080H to 0084H are switched to 1080H to 1084H.
CHAPTER 23 OPTION BYTE (3) 0084H/1084H { On-chip debug operation control • Disabling on-chip debug operation • Enabling on-chip debug operation and erasing data of the flash memory in case authentication of the onchip debug security ID fails • Enabling on-chip debug operation and not erasing data of the flash memory even in case authentication of the on-chip debug security ID fails Caution To use the on-chip debug function, set 02H or 03H to 0084H.
CHAPTER 23 OPTION BYTE 23.2 Format of Option Byte The format of the option byte is shown below. Figure 23-1.
CHAPTER 23 OPTION BYTE Figure 23-1. Format of Option Byte (2/2) Address: 0081H/1081H Notes 1, 2 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 POCMODE POCMODE Notes 1. POC mode selection 0 1.59 V POC mode (default) 1 2.7 V/1.59 V POC mode POCMODE can only be written by using a dedicated flash memory programmer. It cannot be set during self-programming or boot swap operation during self-programming (at this time, 1.59 V POC mode (default) is set).
CHAPTER 23 OPTION BYTE Here is an example of description of the software for setting the option bytes. OPT CSEG OPTION: DB AT 0080H 30H ; Enables watchdog timer operation (illegal access detection operation), ; Window open period of watchdog timer: 50%, ; Overflow time of watchdog timer: 210/fRL, ; Internal low-speed oscillator can be stopped by software. Remark DB 00H ; 1.
CHAPTER 24 FLASH MEMORY The 78K0/LC3 incorporates the flash memory to which a program can be written, erased, and overwritten while mounted on the board. 24.1 Internal Memory Size Switching Register The internal memory capacity can be selected using the internal memory size switching register (IMS). IMS is set by an 8-bit memory manipulation instruction. Reset signal generation sets IMS to CFH. Caution Be sure to set each product to the values shown in Table 24-1 after a reset release. Figure 24-1.
CHAPTER 24 FLASH MEMORY 24.2 Writing with Flash memory programmer Data can be written to the flash memory on-board or off-board, by using a dedicated flash memory programmer. (1) On-board programming The contents of the flash memory can be rewritten after the 78K0/LC3 has been mounted on the target system. The connectors that connect the dedicated flash memory programmer must be mounted on the target system.
CHAPTER 24 FLASH MEMORY Examples of the recommended connection when using the adapter for flash memory writing are shown below. Figure 24-2. Example of Wiring Adapter for Flash Memory Writing in UART (UART6) Mode VDD (2.7 to 5.
CHAPTER 24 FLASH MEMORY 24.3 Programming Environment The environment required for writing a program to the flash memory of the 78K0/LC3 is illustrated below. Figure 24-3. Environment for Writing Program to Flash Memory FLMD0 VDD XXXXXX XXXX STATVE PG-FP4 (Flash Pro4) VSS XXXXX XXXX YYYY Axxxx Bxxxxx Cxxxxxx XXX YYY RS-232C USB RESET Dedicated flash memory programmer 78K0/LC3 UART6 Host machine A host machine that controls the dedicated flash memory programmer is necessary.
CHAPTER 24 FLASH MEMORY The dedicated flash memory programmer generates the following signals for the 78K0/LC3. For details, refer to the user’s manual for the PG-FP4, FL-PR4, PG-FPL3, or FP-LITE3. Table 24-3.
CHAPTER 24 FLASH MEMORY 24.5 Connection of Pins on Board To write the flash memory on-board, connectors that connect the dedicated flash memory programmer must be provided on the target system. First provide a function that selects the normal operation mode or flash memory programming mode on the board. When the flash memory programming mode is set, all the pins not used for programming the flash memory are in the same status as immediately after reset.
CHAPTER 24 FLASH MEMORY (1) Signal collision If the dedicated flash memory programmer (output) is connected to a pin (input) of a serial interface connected to another device (output), signal collision takes place. To avoid this collision, either isolate the connection with the other device, or make the other device go into an output high-impedance state. Figure 24-6.
CHAPTER 24 FLASH MEMORY 24.5.3 RESET pin If the reset signal of the dedicated flash memory programmer is connected to the RESET pin that is connected to the reset signal generator on the board, signal collision takes place. To prevent this collision, isolate the connection with the reset signal generator. If the reset signal is input from the user system while the flash memory programming mode is set, the flash memory will not be correctly programmed.
CHAPTER 24 FLASH MEMORY 24.5.6 Other signal pins Connect X1 and X2 in the same status as in the normal operation mode when using the on-board clock. To input the operating clock from the dedicated flash memory programmer, however, connect as follows. • PG-FP4, FL-PR4: Connect CLK of the programmer to EXCLK/X2/P122. • PG-FPL3, FP-LITE3: Connect CLK of the programmer and X1/P121, and connect its inverted signal to X2/EXCLK/P122.
CHAPTER 24 FLASH MEMORY 24.6 Programming Method 24.6.1 Controlling flash memory The following figure illustrates the procedure to manipulate the flash memory. Figure 24-9. Flash Memory Manipulation Procedure Start FLMD0 pulse supply Flash memory programming mode is set Selecting communication mode Manipulate flash memory No End? Yes End 24.6.
CHAPTER 24 FLASH MEMORY 24.6.3 Selecting communication mode In the 78K0/LC3, a communication mode is selected by inputting pulses to the FLMD0 pin after the dedicated flash memory programming mode is entered. These FLMD0 pulses are generated by the flash memory programmer. The following table shows the relationship between the number of pulses and communication modes. Table 24-6.
CHAPTER 24 FLASH MEMORY 24.6.4 Communication commands The 78K0/LC3 communicates with the dedicated flash memory programmer by using commands. The signals sent from the flash memory programmer to the 78K0/LC3 are called commands, and the signals sent from the 78K0/LC3 to the dedicated flash memory programmer are called response. XXXX XXXXXX Axxxx Bxxxxx XXXXX Cxxxxxx XXX YYY XXXX YYYY Figure 24-11.
CHAPTER 24 FLASH MEMORY 24.7 Security Settings The 78K0/LC3 supports a security function that prohibits rewriting the user program written to the internal flash memory, so that the program cannot be changed by an unauthorized person. The operations shown below can be performed using the Security Set command. The security setting is valid when the programming mode is set next.
CHAPTER 24 FLASH MEMORY Table 24-9. Relationship Between Enabling Security Function and Command (1) During on-board/off-board programming Valid Security Executed Command Batch Erase (Chip Erase) Block Erase Write Note Prohibition of batch erase (chip erase) Cannot be erased in batch Blocks cannot be Can be performed Prohibition of block erase Can be erased in batch. erased. Can be performed. Prohibition of writing . Cannot be performed.
CHAPTER 24 FLASH MEMORY 24.8 Flash Memory Programming by Self-Programming (Under Development) The 78K0/LC3 supports a self-programming function that can be used to rewrite the flash memory via a user program. Because this function allows a user application to rewrite the flash memory by using the 78K0/LC3 self- programming sample library, it can be used to upgrade the program in the field.
CHAPTER 24 FLASH MEMORY The following figure illustrates a flow of rewriting the flash memory by using a self programming sample library. Figure 24-12.
CHAPTER 24 FLASH MEMORY 24.8.1 Boot swap function If rewriting the boot area has failed during self-programming due to a power failure or some other cause, the data in the boot area may be lost and the program may not be restarted by resetting. The boot swap function is used to avoid this problem. Before erasing boot cluster 0 Note , which is a boot program area, by self-programming, write a new boot program to boot cluster 1 in advance.
CHAPTER 24 FLASH MEMORY Figure 24-14.
CHAPTER 25 ON-CHIP DEBUG FUNCTION 25.1 Connecting QB-78K0MINI to 78K0/LC3 The 78K0/LC3 uses the VDD, FLMD0, RESET, OCD0A/X1, OCD0B/X2, and VSS pins to communicate with the host machine via an on-chip debug emulator (QB-78K0MINI). Caution The 78K0/LC3 has an on-chip debug function. Do not use this product for mass production because its reliability cannot be guaranteed after the on-chip debug function has been used, given the issue of the number of times the flash memory can be rewritten.
CHAPTER 25 ON-CHIP DEBUG FUNCTION Connect the FLMD0 pin as follows when performing self programming by means of on-chip debugging. Figure 25-2. Connection of FLMD0 Pin for Self Programming by Means of On-Chip Debugging QB-78K0MINI target connector 78K0/LC3 Port 1 kΩ (recommended) FLMD0 FLMD0 10 kΩ (recommended) 25.
CHAPTER 26 INSTRUCTION SET This chapter lists each instruction set of the 78K0/LC3 in table form. For details of each operation and operation code, refer to the separate document 78K/0 Series Instructions User’s Manual (U12326E). 26.1 Conventions Used in Operation List 26.1.
CHAPTER 26 INSTRUCTION SET 26.1.
CHAPTER 26 INSTRUCTION SET 26.2 Operation List Instruction Group 8-bit data Mnemonic MOV transfer XCH Notes 1.
CHAPTER 26 INSTRUCTION SET Instruction Group 16-bit data Mnemonic MOVW transfer Operands Bytes 3 6 − rp ← word 4 8 10 (saddrp) ← word sfrp, #word 4 − 10 sfrp ← word AX, saddrp 2 6 8 AX ← (saddrp) saddrp, AX 2 6 8 (saddrp) ← AX AX, sfrp 2 − 8 AX ← sfrp sfrp, AX 2 − 8 sfrp ← AX 4 − AX ← rp Z AC CY Note 3 1 rp, AX Note 3 1 4 − rp ← AX 3 10 12 AX ← (addr16) 3 10 12 (addr16) ← AX 1 4 − AX ↔ rp 2 4 − A, CY ← A + byte × × × AX, rp ADD A, #byte
CHAPTER 26 INSTRUCTION SET Instruction Group 8-bit Mnemonic SUB operation Operands Note 2 Flag Z AC CY 2 4 − A, CY ← A − byte × × × 3 6 8 (saddr), CY ← (saddr) − byte × × × Note 3 2 4 − A, CY ← A − r × × × r, A 2 4 − r, CY ← r − A × × × A, saddr 2 4 5 A, CY ← A − (saddr) × × × A, !addr16 3 8 9 A, CY ← A − (addr16) × × × A, [HL] 1 4 5 A, CY ← A − (HL) × × × A, [HL + byte] 2 8 9 A, CY ← A − (HL + byte) × × × A, [HL + B] 2 8 9 A, CY ← A −
CHAPTER 26 INSTRUCTION SET Instruction Group 8-bit Mnemonic OR operation Operands Note 2 Flag Z AC CY 2 4 − A ← A ∨ byte × 3 6 8 (saddr) ← (saddr) ∨ byte × Note 3 2 4 − A←A∨r × r, A 2 4 − r←r∨A × A, saddr 2 4 5 A ← A ∨ (saddr) × A, !addr16 3 8 9 A ← A ∨ (addr16) × A, [HL] 1 4 5 A ← A ∨ (HL) × A, [HL + byte] 2 8 9 A ← A ∨ (HL + byte) × A, [HL + B] 2 8 9 A ← A ∨ (HL + B) × A, [HL + C] 2 8 9 A ← A ∨ (HL + C) × A, #byte 2 4 − A ← A ∨ byte ×
CHAPTER 26 INSTRUCTION SET Instruction Group Mnemonic Operands Bytes Clocks Note 1 Note 2 Operation Flag Z AC CY 16-bit ADDW AX, #word 3 6 − AX, CY ← AX + word × × × operation SUBW AX, #word 3 6 − AX, CY ← AX − word × × × CMPW AX, #word 3 6 − AX − word × × × Multiply/ MULU X 2 16 − AX ← A × X divide DIVUW C 2 25 − AX (Quotient), C (Remainder) ← AX ÷ C Increment/ INC decrement DEC INCW Rotate r 1 2 − r←r+1 × × saddr 2 4 6 (saddr) ← (saddr) +
CHAPTER 26 INSTRUCTION SET Instruction Group Bit Mnemonic AND1 manipulate OR1 XOR1 SET1 CLR1 Notes 1. 2. Operands Bytes Clocks Note 1 Note 2 Operation Flag Z AC CY CY, saddr.bit 3 6 7 CY ← CY ∧ (saddr.bit) × CY, sfr.bit 3 − 7 CY ← CY ∧ sfr.bit × CY, A.bit 2 4 − CY ← CY ∧ A.bit × CY, PSW.bit 3 − 7 CY ← CY ∧ PSW.bit × CY, [HL].bit 2 6 7 CY ← CY ∧ (HL).bit × CY, saddr.bit 3 6 7 CY ← CY ∨ (saddr.bit) × CY, sfr.bit 3 − 7 CY ← CY ∨ sfr.bit × CY, A.
CHAPTER 26 INSTRUCTION SET Instruction Group Call/return Mnemonic Operands Bytes Clocks Note 1 Note 2 Operation CALL !addr16 3 7 − (SP − 1) ← (PC + 3)H, (SP − 2) ← (PC + 3)L, CALLF !addr11 2 5 − (SP − 1) ← (PC + 2)H, (SP − 2) ← (PC + 2)L, Flag Z AC CY PC ← addr16, SP ← SP − 2 PC15 − 11 ← 00001, PC10 − 0 ← addr11, SP ← SP − 2 CALLT [addr5] 1 6 − (SP − 1) ← (PC + 1)H, (SP − 2) ← (PC + 1)L, PCH ← (00000000, addr5 + 1), PCL ← (00000000, addr5), SP ← SP − 2 BRK 1 6 − (SP − 1) ← PSW
CHAPTER 26 INSTRUCTION SET Instruction Group Mnemonic Operands Bytes Clocks Note 1 Operation Note 2 Conditional BT saddr.bit, $addr16 3 8 9 PC ← PC + 3 + jdisp8 if (saddr.bit) = 1 branch sfr.bit, $addr16 4 − 11 PC ← PC + 4 + jdisp8 if sfr.bit = 1 A.bit, $addr16 3 8 − PC ← PC + 3 + jdisp8 if A.bit = 1 PSW.bit, $addr16 3 − 9 PC ← PC + 3 + jdisp8 if PSW.bit = 1 [HL].bit, $addr16 3 10 11 PC ← PC + 3 + jdisp8 if (HL).bit = 1 saddr.
CHAPTER 26 INSTRUCTION SET 26.
CHAPTER 26 INSTRUCTION SET (2) 16-bit instructions MOVW, XCHW, ADDW, SUBW, CMPW, PUSH, POP, INCW, DECW Second Operand #word AX rp Note sfrp saddrp !addr16 SP None First Operand AX ADDW MOVW SUBW XCHW MOVW MOVW MOVW MOVW CMPW rp MOVW MOVW Note INCW DECW PUSH POP sfrp MOVW MOVW saddrp MOVW MOVW !addr16 SP MOVW MOVW MOVW Note Only when rp = BC, DE, HL (3) Bit manipulation instructions MOV1, AND1, OR1, XOR1, SET1, CLR1, NOT1, BT, BF, BTCLR Second Operand A.bit sfr.bit saddr.
CHAPTER 26 INSTRUCTION SET (4) Call instructions/branch instructions CALL, CALLF, CALLT, BR, BC, BNC, BZ, BNZ, BT, BF, BTCLR, DBNZ Second Operand AX !addr16 !addr11 [addr5] $addr16 First Operand Basic instruction BR CALL CALLF CALLT BR BR BC BNC BZ BNZ Compound BT instruction BF BTCLR DBNZ (5) Other instructions ADJBA, ADJBS, BRK, RET, RETI, RETB, SEL, NOP, EI, DI, HALT, STOP 540 User’s Manual U18698EJ1V0UD
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Caution The 78K0/LC3 is provided with an on-chip debug function. After using the on-chip debug function, do not use the product for mass production because its reliability cannot be guaranteed from the viewpoint of the limit of the number of times the flash memory can be rewritten. After the on-chip debug function is used, complaints will not be accepted.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard products Absolute Maximum Ratings (TA = 25°C) (2/2) Parameter Output current, high Symbol IOH1 Conditions Per pin P12, P13, P31 to P34, P40, Ratings Unit −10 mA −25 mA −10 mA −0.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard products X1 Oscillator Characteristics (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V) Resonator Recommended Circuit Ceramic resonator Parameter X1 clock VSS X1 X2 Conditions MIN. TYP. MAX. Unit MHz 2.7 V ≤ VDD ≤ 5.5 V 2.0 10.0 1.8 V ≤ VDD < 2.7 V 2.0 5.0 2.7 V ≤ VDD ≤ 5.5 V 2.0 10.0 1.8 V ≤ VDD < 2.7 V 2.0 5.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard products Internal Oscillator Characteristics (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V) Resonator Parameter 8 MHz internal Internal high-speed oscillation oscillator clock frequency (fRH) RSTS = 1 Notes 1, 2 Conditions MIN. TYP. MAX. Unit 2.5 V ≤ VDD ≤ 5.5 V 7.6 8.0 8.4 MHz 1.8 V ≤ VDD < 2.5 V 6.75 8.0 8.4 MHz RSTS = 0 2.48 5.6 9.86 MHz 240 kHz internal Internal low-speed oscillation 2.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard products DC Characteristics (1/5) (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard products DC Characteristics (2/5) (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, AVREF ≤ VDD, VSS = AVSS = 0 V) Parameter Input voltage, high Input voltage, low Output voltage, high MAX. Unit VIH1 Symbol P32, P100, P101, P112, P121 to P124, P140 to P143, P150 to P153 Conditions 0.7VDD MIN. TYP. VDD V VIH2 P12, P13, P31, P33, P34, P40, P113, P120, RESET, EXCLK 0.8VDD VDD V VIH3 P20 to P25 0.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard products DC Characteristics (3/5) (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, AVREF ≤ VDD, VSS = AVSS = 0 V) Parameter Input leakage current, high Symbol ILIH1 Conditions P12, P13, MIN. TYP. MAX.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard products DC Characteristics (4/5) (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, AVREF ≤ VDD, VSS = AVSS = 0 V) Parameter Supply current Symbol Conditions Operating mode fXH = 10 MHz IDD1 Note 1 Note 2 MIN. , VDD = 5.0 V fXH = 10 MHz Note 2 , VDD = 3.0 V fXH = 5 MHz Note 2 , Note 2 , VDD = 3.0 V fXH = 5 MHz VDD = 2.0 V fRH = 8 MHz, VDD = 5.0 V Note 4 fSUB = 32.768 kHz , TYP. MAX. Unit Square wave input 1.6 3.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard products DC Characteristics (5/5) (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, AVREF ≤ VDD, VSS = AVSS = 0 V) Parameter Watchdog timer Symbol IWDT Note 1 Conditions MIN. TYP. MAX. Unit 5 10 μA 9 18 μA 2.3 V ≤ AVREF ≤ VDD 0.86 1.9 mA VDD = 5.0 V 3.0 8.0 μA VDD = 3.0 V 2.0 5.0 μA VDD = 5.0 V 3.0 8.0 μA VDD = 3.0 V 2.0 5.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard products AC Characteristics (1) Basic operation (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V) Parameter Instruction cycle (minimum Symbol TCY instruction execution time) Conditions MIN. fPRS 2.7 V ≤ VDD ≤ 5.5 V 0.2 16 μs 1.8 V ≤ VDD < 2.7 V 0.4 16 μs 125 μs 2.7 V ≤ VDD ≤ 5.5 V 10 MHz 1.8 V ≤ VDD < 2.7 V 5 MHz XSEL = 1 XSEL = 0 2.7 V ≤ VDD ≤ 5.5 V fEXCLK 114 122 7.6 8.4 MHz 6.75 8.4 MHz 2.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard products TCY vs. VDD (Main System Clock Operation) Cycle time TCY [ μ s] 100 16 10 5.0 2.0 Guaranteed operation range 1.0 0.4 0.2 0.1 0.01 0 1.0 2.0 3.0 5.0 5.5 6.0 4.0 2.7 1.8 Supply voltage VDD [V] AC Timing Test Points (Excluding External Main System Clock) VIH VIH Test points VIL VIL External Main System Clock Timing 1/fEXCLK tEXCLKL tEXCLKH 0.8VDD (MIN.) EXCLK 0.2VDD (MAX.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard products TI Timing tTIH0 tTIL0 TI000 1/fTI5 tTIL5 tTIH5 TI52 Interrupt Request Input Timing tINTH tINTL INTP0-INTP3 Key Interrupt Input Timing tKR KR0, KR3, KR4 RESET Input Timing tRSL RESET 552 User’s Manual U18698EJ1V0UD
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard products (2) Manchester code generator (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Conditions MIN. TYP. Transfer rate MAX. Unit 250 kbps MAX. Unit 625 kbps MAX. Unit 625 kbps (3) Serial interface (TA = −40 to +85°C, 1.8 V ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V) (a) UART6 (Dedicated baud rate generator output) Parameter Symbol Conditions MIN. TYP.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard products 10-bit successive approximation type A/D Converter Characteristics (μPD78F041x only) (TA = −40 to +85°C, 2.3 V ≤ AVREF ≤ VDD ≤ 5.5 V, VSS = AVSS = 0 V) Parameter Symbol Resolution Overall error AINL Conversion time tCONV Notes 1, 2 Zero-scale error EZS Notes 1, 2 Full-scale error Integral non-linearity error EFS Note 1 Differential non-linearity error Analog input voltage 2. 554 MIN. MAX. Unit 10 bit 4.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard products LCD Characteristics (1) Resistance division method (a) Static display mode (TA = −40 to +85°C, 1.8 V ≤ VLCD ≤ VDD ≤ 5.5 V, VSS = 0 V)Note 3 Parameter LCD drive voltage Symbol VLCD Conditions MIN. TYP. Note 3 MAX. Unit VDD V Note 1 RLCD 150 kΩ LCD output resistor (Common) Note 2 RODC 40 kΩ LCD output resistor (Segment) Note 2 RODS 200 kΩ MAX.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard products 1.59 V POC Circuit Characteristics (TA = −40 to +85°C, VSS = 0 V) Parameter Symbol Detection voltage VPOC Power supply voltage rise tPTH Conditions VDD: 0 V → change inclination of VPOC MIN. TYP. MAX. Unit 1.44 1.59 1.74 V 0.5 V/ms 200 μs inclination Minimum pulse width tPW POC Circuit Timing Supply voltage (VDD) Detection voltage (MAX.) Detection voltage (TYP.) Detection voltage (MIN.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard products LVI Circuit Characteristics (TA = −40 to +85°C, VPOC ≤ VDD ≤ 5.5 V, VSS = 0 V) Parameter Detection Symbol Supply voltage level voltage External input pin Note 1 Minimum pulse width MIN. TYP. MAX. Unit VLVI0 4.14 4.24 4.34 V VLVI1 3.99 4.09 4.19 V VLVI2 3.83 3.93 4.03 V VLVI3 3.68 3.78 3.88 V VLVI4 3.52 3.62 3.72 V VLVI5 3.37 3.47 3.57 V VLVI6 3.22 3.32 3.42 V VLVI7 3.06 3.16 3.
CHAPTER 27 ELECTRICAL SPECIFICATIONS (STANDARD PRODUCTS) Standard products Data Memory STOP Mode Low Supply Voltage Data Retention Characteristics (TA = −40 to +85°C) Parameter Data retention supply voltage Symbol Conditions MIN. VDDDR 1.44 TYP. Note MAX. Unit 5.5 V Note The value depends on the POC detection voltage. When the voltage drops, the data is retained until a POC reset is effected, but data is not retained when a POC reset is effected.
CHAPTER 28 PACKAGE DRAWINGS 48-PIN PLASTIC LQFP (FINE PITCH) (7x7) HD D detail of lead end 36 A3 25 37 c 24 θ L Lp E L1 HE (UNIT:mm) 13 48 1 12 ZE e ZD b x M S A A2 A1 S NOTE Each lead centerline is located within 0.08 mm of its true position at maximum material condition. User’s Manual U18698EJ1V0UD DIMENSIONS 7.00±0.20 E 7.00±0.20 HD 9.00±0.20 HE 9.00±0.20 A 1.60 MAX. A1 0.10±0.05 A2 1.40±0.05 A3 0.25 +0.07 0.20 −0.03 b S y ITEM D c 0.125 +0.075 −0.025 L 0.
CHAPTER 29 CAUTIONS FOR WAIT 29.1 Cautions for Wait This product has two internal system buses. One is a CPU bus and the other is a peripheral bus that interfaces with the low-speed peripheral hardware. Because the clock of the CPU bus and the clock of the peripheral bus are asynchronous, unexpected illegal data may be passed if an access to the CPU conflicts with an access to the peripheral hardware.
CHAPTER 29 CAUTIONS FOR WAIT 29.2 Peripheral Hardware That Generates Wait Table 29-1 lists the registers that issue a wait request when accessed by the CPU, and the number of CPU wait clocks. Table 29-1.
For further information, please contact: NEC Electronics Corporation 1753, Shimonumabe, Nakahara-ku, Kawasaki, Kanagawa 211-8668, Japan Tel: 044-435-5111 http://www.necel.com/ [America] [Europe] [Asia & Oceania] NEC Electronics America, Inc. 2880 Scott Blvd. Santa Clara, CA 95050-2554, U.S.A. Tel: 408-588-6000 800-366-9782 http://www.am.necel.com/ NEC Electronics (Europe) GmbH Arcadiastrasse 10 40472 Düsseldorf, Germany Tel: 0211-65030 http://www.eu.necel.com/ NEC Electronics (China) Co.
