Datasheet

Data Sheet S16265EJ5V0DS

PD720101

PCI Bus Interface : handles 32-bit 33 MHz PCI bus master and target function which comply with PCI

specification release 2.2. The number of enabled ports is set by bit in configuration

space.

Arbiter : arbitrates among two OHCI host controller cores and one EHCI host controller core.

OHCI Host Controller #1 : handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 1, 3, and 5.

OHCI Host Controller #2 : handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 2 and 4.

EHCI Host Controller : handles high- (480 Mbps) signaling at port 1, 2, 3, 4, and 5.

Root Hub : handles USB hub function in host controller and controls connection (routing) between

host controller core and port.

PHY : consists of high-speed transceiver, full-/low-speed transceiver, serializer, deserializer,

etc.

INTA0 : is the PCI interrupt signal for OHCI Host Controller #1.

INTB0 : is the PCI interrupt signal for OHCI Host Controller #2.

INTC0 : is the PCI interrupt signal for EHCI Host Controller.

SMI0 : is the interrupt signal which is specified by Open Host Controller Interface Specification

for USB Rev 1.0a and Enhanced Host Controller Interface Specification Rev 1.0. The

SMI signal of each OHCI Host Controller and EHCI Host Controller appears at this

signal.

PME0 : is the interrupt signal which is specified by PCI-Bus Power Management Interface

Specification release 1.1. Wakeup signal of each host controller core appears at this

signal.

COMPARISON WITH THE

PD720100A

PD720101 (2nd generation)

EHCI revision 0.95 1.0

EHCI 1 1

OHCI 2 2

Legacy support Parallel IRQ out support No parallel IRQ support

Clock 48 MHz OSC or 30 MHz OSC/X’tal 48 MHz OSC or 30 MHz X’tal

Package 176-pin BGA (FP) or 160-pin LQFP 144-pin BGA (FP) or 144-pin LQFP