Datasheet

Data Sheet S16265EJ5V0DS
26
µ PD720101
3.4 Timing Diagram
PCI clock
0.4V DD
0.6V DD
0.2V DD
0.5V DD
0.3V DD
0.4V DD (ptp:min)
t
cyc
t high t low
PCI reset
PCLK
PWR_GOOD
VBBRST0
100 ms (typ.)
t rst
t rst-off
PCI Signals Valid
t rst-clk