Datasheet

Data Sheet S16265EJ5V0DS
9
µ PD720101
(2/2)
Pin Name I/O Buffer Type Active
Level
Function
SMC I Input with 50 kΩ pull down R High Scan mode control
TEB I Input with 50 kΩ pull down R High BIST enable
AMC I Input with 50 kΩ pull down R High ATG mode control
TEST I Input with 50 kΩ pull down R High Test control
NANDTEST I Input with 50 kΩ pull down R High NAND tree test enable
AVDD VDD for analog circuit
VDD VDD
VDD_PCI 5 V (5 V PCI) or 3.3 V (3.3 V PCI)
AVSS VSS for analog circuit
VSS VSS
N.C. No connection
Remarks 1. “5 V tolerant“ means that the buffer is 3 V buffer with 5 V tolerant circuit.
2. “5 V PCI” indicates a PCI buffer, which complies with the 3 V PCI standard, has a 5 V tolerant circuit. It
does not indicate that this buffer fully complies with 5 V PCI standard. However, this function can be
used for evaluating the operation of a device on a 5 V add-in card.
3. The signal marked as “(I/O)” in the above table operates as I/O signals during testing. However, they
do not need to be considered in normal use.