Datasheet

Data Sheet S16265EJ5V0DS
8
µ PD720101
1. PIN INFORMATION
(1/2)
Pin Name I/O Buffer Type Active
Level
Function
AD (31 : 0) I/O 5 V PCI I/O PCI “AD [31 : 0]” signal
CBE (3 : 0)0 I/O 5 V PCI I/O PCI “C/BE [3 : 0]” signal
PAR I/O 5 V PCI I/O PCI “PAR” signal
FRAME0 I/O 5 V PCI I/O PCI “FRAME#” signal
IRDY0 I/O 5 V PCI I/O PCI “IRDY#” signal
TRDY0 I/O 5 V PCI I/O PCI “TRDY#” signal
STOP0 I/O 5 V PCI I/O PCI “STOP#” signal
IDSEL I 5 V PCI input PCI “IDSEL” signal
DEVSEL0 I/O 5 V PCI I/O PCI “DEVSEL#” signal
REQ0 O 5 V PCI output PCI “REQ#” signal
GNT0 I 5 V PCI input PCI “GNT#” signal
PERR0 I/O 5 V PCI I/O PCI “PERR#” signal
SERR0 O 5 V PCI N-ch open drain PCI “SERR#” signal
INTA0 O 5 V PCI N-ch open drain Low PCI “INTA#” signal
INTB0 O 5 V PCI N-ch open drain Low PCI “INTB#” signal
INTC0 O 5 V PCI N-ch open drain Low PCI “INTC#” signal
PCLK I 5 V PCI input PCI “CLK” signal
VBBRST0 I 5 V tolerant input Low Hardware reset for chip
CRUN0 I/O 5 V PCI I/O PCI “CLKRUN#” signal
PME0 O 5 V PCI N-ch open drain Low PCI “PME#” signal
VCCRST0 I 5 V tolerant input Low Reset for power management
SMI0 O 5 V tolerant N-ch open drain Low System management interrupt output
XT1/SCLK I Input System clock input or oscillator in
XT2 O Output oscillator out
DP (5 : 1) I/O USB high speed D+ I/O USB high speed D+ signal
DM (5 : 1) I/O USB high speed D− I/O USB high speed D− signal
RSDP (5 : 1) O USB full speed D+ Output USB full speed D+ signal
RSDM (5 : 1) O USB full speed D− Output USB full speed D− signal
OCI (5 : 1) I (I/O) Input Low USB root hub port’s overcurrent status input
PPON (5 : 1) O (I/O) Output High USB root hub port’s power supply control output
LEGC I (I/O) Input High Legacy support switch
SRCLK O Output Serial ROM clock out
SRDTA I/O I/O Serial ROM data
SRMOD I Input with 50 kΩ pull down R High Serial ROM input enable
RREF A Analog Reference resistor
NTEST1 I Input with 12 kΩ pull down R High Test pin