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DATA SHEET MOS INTEGRATED CIRCUIT µPD720101 USB 2.0 HOST CONTROLLER The µPD720101 complies with the Universal Serial Bus Specification Revision 2.0 and Open Host Controller Interface Specification for full-/low-speed signaling and Intel's Enhanced Host Controller Interface Specification for high-speed signaling and works up to 480 Mbps. The µPD720101 is integrated 3 host controller cores with PCI interface and USB 2.0 transceivers into a single chip.
µPD720101 BLOCK DIAGRAM PCI Bus PME0 INTA0 INTB0 INTC0 PCI Bus Interface WakeUp_Event WakeUp_Event WakeUp_Event Arbiter OHCI Host Controller #1 OHCI Host Controller #2 EHCI Host Controller SMI0 Root Hub PHY Port 1 Port 2 Port 3 Port 4 USB Bus Remark INTB0/INTC0 can be shared with INTA0 through BIOS setting.
µPD720101 PCI Bus Interface : handles 32-bit 33 MHz PCI bus master and target function which comply with PCI specification release 2.2. The number of enabled ports is set by bit in configuration space. Arbiter : arbitrates among two OHCI host controller cores and one EHCI host controller core. OHCI Host Controller #1 : handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 1, 3, and 5. OHCI Host Controller #2 : handles full- (12 Mbps)/low-speed (1.5 Mbps) signaling at port 2 and 4.
µPD720101 PIN CONFIGURATION • 144-pin plastic LQFP (Fine pitch) (20 × 20) µPD720101GJ-UEN µPD720101GJ-UEN-A 110 115 120 125 130 135 140 1 105 5 100 10 95 15 90 20 85 25 80 30 75 70 65 60 55 50 VSS VSS AD23 AD22 AD21 AD20 VDD AD19 AD18 AD17 AD16 CBE20 FRAME0 IRDY0 TRDY0 DEVSEL0 STOP0 VSS VDD VDD_PCI PERR0 SERR0 PAR CBE10 AD15 AD14 AD13 AD12 AD11 AD10 AD9 AD8 CBE00 AD7 VSS VSS 45 35 40 VDD VDD OCI1 PPON1 OCI2 PPON2 OCI3 PPON3 OCI4 PPON4 OCI5 PPON5 VCCRST0 PME0 PCLK VBBRST0 VDD_PCI VS
µPD720101 Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
µPD720101 • 144-pin plastic FBGA (12 × 12) µPD720101F1-EA8 µPD720101F1-EA8-A Bottom View 25 26 27 28 29 30 31 32 33 34 35 36 24 71 72 73 74 75 76 77 78 79 80 81 82 37 13 23 70 111 112 113 114 115 116 117 118 119 120 83 38 12 22 69 110 137 138 139 140 121 84 39 11 21 68 109 122 85 40 10 20 67 108 136 141 123 86 41 9 19 66 107 135 142 124 87 42 8 18 65 106 134 143 125 88 43 7 17 64 105 133 144 126 89 44 6 16 63
µPD720101 Pin No. Pin Name Pin No. Pin Name Pin No. Pin Name Pin No.
µPD720101 1.
µPD720101 (2/2) Pin Name I/O Buffer Type Active Function Level SMC I Input with 50 kΩ pull down R High Scan mode control TEB I Input with 50 kΩ pull down R High BIST enable AMC I Input with 50 kΩ pull down R High ATG mode control TEST I Input with 50 kΩ pull down R High Test control NANDTEST I Input with 50 kΩ pull down R High NAND tree test enable AVDD VDD for analog circuit VDD VDD VDD_PCI 5 V (5 V PCI) or 3.3 V (3.3 V PCI) AVSS VSS for analog circuit VSS VSS N.C.
µPD720101 2. 2.1 HOW TO CONNECT TO EXTERNAL ELEMENTS Handling Unused Pins To realize less than 5 ports host controller implementation, appropriate value shall be set to Port No field in EXT1 register. And unused pins shall be connected as shown below. Pin 2.2 Direction Connection Method DPx I/O Tied to "low". DMx I/O Tied to "low". RSDPx O No connection (Open) RSDMx O No connection (Open) OCIx I “H” clamp PPONx O No connection (Open) USB Port Connection Figure 2-1.
µPD720101 2.3 PLL Capacitor Connection Figure 2-2. RREF Connection LSI RREF 9.1kΩ ±1% AVSS(R) AVSS 2.4 X’tal Connection Figure 2-3. X’tal Connection LSI XT1/SCLK R X'tal XT2 C2 C1 Vss The following crystals are evaluated on our reference design board. Table 2-1 shows the external parameters.
µPD720101 Table 2-1. External Parameters Vender KDS Note 1 NDK Note 2 X’tal R C1 C2 AT-49 30.000 MHz 100 Ω 12 pF 10 pF AT-41 30.000 MHz 100 Ω 10 pF 10 pF AT-41CD2 30.000 MHz 100 Ω 10 pF 10 pF NX3225DA 30.000 MHz 100 Ω 10 pF 10 pF NX5032GA 30.000 MHz 100 Ω 10 pF 10 pF NX8045GB 30.000 MHz 100 Ω 10 pF 10 pF Notes 1. DAISHINKU CORP. 2. NIHON DEMPA KOGYO CO., LTD.
µPD720101 3. ELECTRICAL SPECIFICATIONS 3.
µPD720101 3.2 Terminology Terms Used in Absolute Maximum Ratings Parameter Power supply voltage Input voltage Symbol Meaning VDD, AVDD, Indicates voltage range within which damage or reduced reliability will not VDD_PCI result when power is applied to a VDD pin. VI Indicates voltage range within which damage or reduced reliability will not result when power is applied to an input pin.
µPD720101 3.3 Electrical Specifications Absolute Maximum Ratings Parameter Power supply voltage Input voltage, 5 V buffer Symbol Condition Rating Unit VDD −0.5 to +4.6 V AVDD −0.5 to +4.6 V VDD_PCI −0.5 to +6.0 V −0.5 to +6.6 V −0.5 to +4.6 V −0.5 to +6.6 V −0.5 to +4.6 V 3.0 V ≤ VDD ≤ 3.6 V VI VI < VDD + 3.0 V Input voltage, 3.3 V buffer 3.0 V ≤ VDD ≤ 3.6 V VI VI < VDD + 0.5 V Output voltage, 5 V buffer 3.0 V ≤ VDD ≤ 3.6 V VO VO < VDD + 3.0 V Output voltage, 3.
µPD720101 DC Characteristics (VDD = 3.0 to 3.6 V, TA = 0 to +70°C) Control pin block Parameter Off-state output current Symbol IOZ Output short circuit current IOS Low-level output current IOL Condition Min. VO = VDD or VSS Note Max. Unit ±10 µA −250 mA 3.3 V low-level output current VOL = 0.4 V 9.0 mA 3.3 V low-level output current VOL = 0.4 V 3.0 mA 5.0 V low-level output current VOL = 0.4 V 12.0 mA 5.0 V low-level output current VOL = 0.4 V 6.0 mA 3.
µPD720101 USB interface block Parameter Serial resistor between DP (DM) and Symbol Conditions RS Min. Max. Unit 35.64 36.36 Ω 40.5 49.5 Ω RSDP (RSDM) Output pin impedance ZHSDRV Includes RS resistor Input Levels for Low-/full-speed: High-level input voltage (drive) VIH 2.0 V High-level input voltage (floating) VIHZ 2.7 Low-level input voltage VIL Differential input sensitivity VDI (D+) − (D−) 0.2 Differential common mode range VCM Includes VDI range 0.8 2.
µPD720101 Figure 3-1. Differential Input Sensitivity Range for Low-/full-speed Differential Input Voltage Range Differential Output Crossover Voltage Range −1.0 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0 3.2 Input Voltage Range (V) Figure 3-2. Full-speed Buffer VOH/IOH Characteristics for High-speed Capable Transceiver VDD−3.3 VDD−2.8 VDD−2.3 VDD−1.8 VDD−1.3 VDD−0.8 VDD−0.3 VDD 0 IOUT (mA) −20 −40 Min. −60 Max. −80 VOUT (V) Figure 3-3.
µPD720101 Figure 3-4. Receiver Sensitivity for Transceiver at DP/DM Level 1 +400 mV Differential Point 3 Point 4 Point 1 0V Differential Point 2 Point 6 Point 5 −400 mV Differential Level 2 Unit Interval 0% 100% Figure 3-5. Receiver Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device Vbus D+ DGnd 50 Ω Coax 15.
µPD720101 Power consumption Parameter Symbol Condition Typ. Typ. Unit (30 MHz X’tal) (48 MHz OSC) Power Consumption PWD0-0 Device state = D0, All the ports does not connect to 31.4 10.4 mA any function, and each OHCI controller is under Note1 UsbSuspend and EHCI controller is stopped. PWD0-2 The power consumption under the state without suspend. Device state = D0, The number of active Note2 ports is 2. PWD0-3 Full- or low-speed device(s) is (are) on the port. 53.1 31.
µPD720101 System clock ratings Parameter Clock frequency Symbol fCLK Condition X’tal Min. Typ. Max. Unit −500 30 +500 MHz ppm Oscillator block −500 ppm 48 ppm Clock duty cycle tDUTY 40 +500 MHz ppm 50 60 % Remarks 1. Recommended accuracy of clock frequency is ± 100 ppm. 2. Required accuracy of X’tal or oscillator block is including initial frequency accuracy, the spread of X’tal capacitor loading, supply voltage, temperature, and aging, etc.
µPD720101 AC Characteristics (VDD = 3.0 to 3.6 V, TA = 0 to +70°C) PCI interface block Parameter Symbol Condition Min. Max. Unit PCI clock cycle time tcyc 30 ns PCI clock pulse, high-level width thigh 11 ns PCI clock pulse, low-level width tlow 11 ns PCI clock, rise slew rate Scr 0.2VDD to 0.6VDD 1 4 V/ns PCI clock, fall slew rate Scf 0.2VDD to 0.6VDD 1 4 V/ns PCI reset active time (vs. power supply trst 1 ms 100 µs stability) PCI reset active time (vs.
µPD720101 USB interface block (1/2) Parameter Symbol Conditions Min. Max. Unit 75 300 ns 75 300 ns 80 125 % 1.49925 1.50075 Mbps tDDJ1 tDDJ2 −25 −14 +25 +14 ns ns tLDEOP −40 +100 ns To next transition For paired transitions tUJR1 tUJR2 −152 −200 +152 +200 ns ns Source SE0 interval of EOP tLEOPT 1.25 1.
µPD720101 (2/2) Parameter Symbol Conditions Min. Max. Unit High-speed Source Electrical Characteristics Rise time (10 to 90%) tHSR 500 ps Fall time (90 to 10%) tHSF 500 ps Driver waveform See Figure 3-6. High-speed data rate tHSDRAT 479.760 480.240 Mbps Microframe interval tHSFRAM 124.9375 125.0625 µs Consecutive microframe interval difference tHSRFI Data source jitter See Figure 3-6. Receiver jitter tolerance See Figure 3-4.
µPD720101 Figure 3-6. Transmit Waveform for Transceiver at DP/DM +400 mV Differential Level 1 Point 3 Point 4 Point 1 0V Differential Point 2 Point 5 Point 6 −400 mV Differential Level 2 Unit Interval 0% 100% Figure 3-7. Transmitter Measurement Fixtures Test Supply Voltage 15.8 Ω USB Connector Nearest Device Vbus D+ DGnd 15.
µPD720101 3.4 Timing Diagram PCI clock tcyc thigh tlow 0.6VDD 0.5VDD 0.4VDD 0.3VDD 0.2VDD 0.4VDD (ptp:min) PCI reset PCLK 100 ms (typ.
µPD720101 PCI output timing measurement condition 0.6VDD PCLK 0.4VDD 0.2VDD tval , tval (ptp) 0.615VDD (for falling edge) Output delay 0.285VDD (for falling edge) Output ton toff PCI input timing measurement condition 0.6VDD 0.4VDD PCLK 0.2VDD tsu , tsu (ptp) th 0.6VDD Input 0.4VDD 0.
µPD720101 USB differential data jitter for full-speed tPERIOD Differential Data Lines Crossover Points Consecutive Transitions N × tPERIOD + txDJ1 Paired Transitions N × tPERIOD + txDJ2 USB differential-to-EOP transition skew and EOP width for low-/full-speed tPERIOD Differential Data Lines Crossover Point Extended Crossover Point Diff.
µPD720101 Low-/full-speed disconnect detection D+/D− VIZH (min) VIL D−/D+ VSS tDDIS Device Disconnected Disconnect Detected Full-/high-speed device connect detection D+ VIH D− VSS tDCNN Device Connected Connect Detected Low-speed device connect detection D− VIH D+ VSS tDCNN Device Connected Connect Detected Data Sheet S16265EJ5V0DS 29
µPD720101 4. PACKAGE DRAWINGS 144-PIN PLASTIC LQFP (FINE PITCH) (20x20) A B 108 109 73 72 detail of lead end S C D R Q 144 1 37 36 F G H I J M K P S N S L M NOTE Each lead centerline is located within 0.08 mm of its true position (T.P.) at maximum material condition. ITEM A MILLIMETERS 22.0±0.2 B C 20.0±0.2 20.0±0.2 D 22.0±0.2 F 1.25 G 1.25 H 0.22±0.05 I 0.08 J 0.5 (T.P.) K 1.0±0.2 L 0.5±0.2 M 0.17 +0.03 −0.07 N P 0.08 1.4 Q 0.10±0.05 R 3° +4° −3° S 1.5±0.
µPD720101 144-PIN PLASTIC FBGA (12x12) ZD E B ZE w S B 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A D INDEX MARK P NM L K J HG F E D C B A w S A A y1 A2 S S y S e φb φx M A1 S AB ITEM D MILLIMETERS 12.00±0.10 E 12.00±0.10 w 0.20 A 1.48±0.10 A1 0.35±0.06 A2 1.13 e 0.80 b 0.50 +0.05 –0.10 x 0.08 y 0.10 y1 0.20 ZD 0.80 ZE Data Sheet S16265EJ5V0DS 0.
µPD720101 5. RECOMMENDED SOLDERING CONDITIONS The µPD720101 should be soldered and mounted under the following recommended conditions. For soldering methods and conditions other than those recommended below, contact an NEC Electronics sales representative. For technical information, see the following website. Semiconductor Device Mount Manual (http://www.necel.com/pkg/en/mount/index.
µPD720101 [MEMO] Data Sheet S16265EJ5V0DS 33
µPD720101 [MEMO] 34 Data Sheet S16265EJ5V0DS
µPD720101 NOTES FOR CMOS DEVICES 1 VOLTAGE APPLICATION WAVEFORM AT INPUT PIN Waveform distortion due to input noise or a reflected wave may cause malfunction. If the input of the CMOS device stays in the area between VIL (MAX) and VIH (MIN) due to noise, etc., the device may malfunction. Take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between VIL (MAX) and VIH (MIN).
µPD720101 USB logo is a trademark of USB Implementers Forum, Inc. Windows is either a registered trademark or a trademark of Microsoft Corporation in the United States and/or other countries. • The information in this document is current as of Macrh, 2005. The information is subject to change without notice. For actual design-in, refer to the latest publications of NEC Electronics data sheets or data books, etc., for the most up-to-date specifications of NEC Electronics products.
