Datasheet

V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 999 of 1513
Aug 12, 2011
(2) Status in CAN sleep mode
The CAN module is in one of the following states after it enters the CAN sleep mode.
• The internal operating clock is stopped and the power consumption is minimized.
• The function to detect the falling edge of the CAN reception pin (CRXD0) remains in effect to wake up the CAN
module from the CAN bus.
• To wake up the CAN module from the CPU, data can be written to the PSMODE1 and PSMODE0 bits, but
nothing can be written to other CANn module registers or bits.
• The CAN0 module registers can be read, except for the C0LIPT, C0RGPT, C0LOPT, and C0TGPT registers.
• The CAN0 message buffer registers cannot be written or read.
• C0GMCTRL.MBON bit is cleared to 0.
• A request for transition to the initialization mode is not acknowledged and is ignored.
(3) Releasing CAN sleep mode
The CAN sleep mode is released by the following events.
• When the CPU writes 00B to the PSMODE1 and PSMODE0 bits
• A falling edge at the CAN reception pin (CRXD0) (i.e. the CAN bus level shifts from recessive to dominant)
Cautions1. Even if the falling edge belongs to the SOF of a receive message, this message will not be
received and stored. If the CPU has turned off the clock to the CAN while the CAN was in sleep
mode, later on the CAN sleep mode will not be released and PSMODE[1:0] bits will continue to
be 01B unless the clock for the CAN is provided again. In addition to this, the receive message
will not be received afterwards.
Caution2. If a falling edge is detected at the CAN reception pin (CRXD0) while the CAN clock is supplied,
the PSMODE0 bit must be cleared by software. (For details, refer to the processing in Figure 20-
53.)
After releasing the sleep mode, the CAN module returns to the operation mode from which the CAN sleep mode was
requested and the PSMODE1 and PSMODE0 bits are reset to 00B. If the CAN sleep mode is released by a change in the
CAN bus state, the C0INTS.CINTS5 bit is set to 1, regardless of the C0IE.CIE bit. After the CAN module is released from
the CAN sleep mode, it participates in the CAN bus again by automatically detecting 11 consecutive recessive-level bits
on the CAN bus. After releasing the sleep mode and before accessing the message buffer by application again, confirm
that C0GMCTRL.MBON bit = 1.
When a request for transition to the initialization mode is made while the CAN module is in the CAN sleep mode, that
request is ignored; the CPU has to be released from sleep mode by software first before entering the initialization mode.
Caution When the CAN sleep mode is released by an event of the CAN bus, a wakeup interrupt occurs
even if the event of the CAN bus occurs immediately after the mode has been changed to the
sleep mode. Note that the interrupt can occur at any time.