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ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 32-Bit 48 MHz I/O number 77
9919929939949959969979989991000
V850ES/JG3-H, V850ES/JH3-H CHAPTER 20 CAN CONTROLLER
R01UH0042EJ0500 Rev.5.00 Page 995 of 1513
Aug 12, 2011
Cautions 1. To resume the normal operation mode with ABT from the message buffer 0, set the ABTCLR bit to
1 while the ABTTRG bit is cleared to 0. If the ABTCLR bit is set to 1 while the ABTTRG bit is set to
1, the subsequent operation is not guaranteed.
2. Whether the automatic block transmission engine is cleared by setting the ABTCLR bit to 1 can
be confirmed if the ABTCLR bit is automatically cleared to 0 immediately after the processing of
the clearing request is completed.
3. Do not set the ABTTRG bit in the initialization mode. If the ABTTRG bit is set in the initialization
mode, the proper operation is not guaranteed after the mode is changed from the initialization
mode to the ABT mode.
4. Do not set the TRQ bit of the ABT message buffers to 1 by software in the normal operation mode
with ABT. Otherwise, the operation is not guaranteed.
5. The C0GMABTD register is used to set the delay time that is inserted in the period from
completion of the preceding ABT message to setting of the TRQ bit for the next ABT message
when the transmission requests are set in the order of message numbers for each message for
ABT that is successively transmitted in the ABT mode. The timing at which the messages are
actually transmitted onto the CAN bus varies depending on the status of transmission from other
stations and the status of the setting of the transmission request for messages other than the
ABT messages (message buffers 8 to 31).
6. If a transmission request is made for a message other than an ABT message and if no delay time
is inserted in the interval in which transmission requests for ABT are automatically set
(C0GMABTD register = 00H), messages other than ABT messages may be transmitted regardless
of their priority in regards to the ABT message.
7. Do not clear the RDY bit to 0 when the ABTTRG bit = 1.
8. If a message is received from another node in the normal operation mode with ABT, the message
may be transmitted after the time of one frame has elapsed even when C0GMABTD register = 00H.
Remark m = 00 to 31