Datasheet

ManualsBrandsRENESAS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller LQFP 100 32-Bit 48 MHz I/O number 77

100

V850ES/JG3-H, V850ES/JH3-H CHAPTER 3 CPU FUNCTION

R01UH0042EJ0500 Rev.5.00 Page 98 of 1513

Aug 12, 2011

(2/2)

Peripheral Function Register Name Access k

C00 to I

C02 IICS0 to IICS2 Read 1

CRC CRCD Write 1

C0GMABT,

C0GMABTD,

C0MASKaL, C0MASKaH,

C0LEC,

C0INFO,

C0ERC,

C0IE,

C0INTS,

C0BRP,

C0BTR,

C0TS

Read/Write

XX/fCANMOD + 1) / (2 + j) (MIN.)

Note

(2 × f

XX/fCANMOD + 1) / (2 + j) (MAX.)

Note

C0GMCTRL,

C0GMCS,

C0CTRL

Read/Write

XX/fCAN + 1) / (2 + j) (MIN.)

Note

(2 × f

XX/fCAN + 1) / (2 + j) (MAX.)

Note

Write

XX/fCANMOD + 1) / (2 + j) (MIN.)

Note

(2 × f

XX/fCANMOD + 1) / (2 + j) (MAX.)

Note

C0RGPT,

C0TGPT

Read

(3 × f

XX/fCANMOD + 1) / (2 + j) (MIN.)

Note

(4 × fXX/fCANMOD + 1) / (2 + j) (MAX.)

Note

C0LIPT,

C0LOPT

Read

(3 × f

XX/fCANMOD + 1) / (2 + j) (MIN.)

Note

(4 × fXX/fCANMOD + 1) / (2 + j) (MAX.)

Note

Write

(4 × f

XX/fCAN + 1) / (2 + j) (MIN.)

Note

(5 × fXX/fCAN + 1) / (2 + j) (MAX.)

Note

C0MCTRLm

Read

(3 × f

XX/fCAN + 1) / (2 + j) (MIN.)

Note

(4 × fXX/fCAN + 1) / (2 + j) (MAX.)

Note

Write (8 bits)

(4 × f

XX/fCANMOD + 1) / (2 + j) (MIN.)

Note

(5 × fXX/fCANMOD + 1) / (2 + j) (MAX.)

Note

Write (16 bits)

(2 × f

XX/fCANMOD + 1) / (2 + j) (MIN.)

Note

(3 × fXX/fCANMOD + 1) / (2 + j) (MAX.)

Note

CAN controller

(m = 0 to 31, a = 1 to 4)

C0MDATA01m, C0MDATA0m,

C0MDATA1m, C0MDATA23m,

C0MDATA2m, C0MDATA3m,

C0MDATA45m, C0MDATA4m,

C0MDATA5m, C0MDATA67m,

C0MDATA6m, C0MDATA7m,

C0MDLCm,

C0MCONFm,

C0MIDLm,

C0MIDHm

Read (8/16 bits)

(3 × f

XX/fCANMOD + 1) / (2 + j) (MIN.)

Note

(4 × fXX/fCANMOD + 1) / (2 + j) (MAX.)

Note

Number of clocks necessary for access = 3 + i + j + (2 + j) × k

Note Digits below the decimal point are rounded up.

Caution Accessing the above registers is prohibited in the following statuses. If a wait cycle is generated,

it can only be cleared by a reset.

• When the CPU operates with the subclock and the main clock oscillation is stopped

• When the CPU operates with the internal oscillation clock

Remark i: Values (0) of higher 4 bits of VSWC register

j: Values (0 or 1) of lower 4 bits of VSWC register